LDPC Bit Interleaver Permutation for 64-Symbol Burst Error Distribution

The patent divides the LDPC codeword into multiple bit groups (e.g., 45 groups of 360 bits each) and performs interleaving at the bit group level rather than individual bit level. This segmentation allows the system to maintain bandwidth efficiency while effectively distributing burst errors across different bit groups, preventing concentrated error patterns that would degrade performance.

The patent introduces a new dimension of interleaving operation by using bit group-based permutation instead of traditional bit-by-bit interleaving. By organizing codeword bits into structured groups and applying permutation operations at this higher level, the system achieves both efficiency and robustness against burst errors through dimensional transformation of the interleaving process.

The patent optimizes performance by adjusting key parameters such as bit group size (360 bits), number of bit groups (45), and specific permutation sequences. These parameter changes are tailored to match specific modulation orders (e.g., 64-QAM) and LDPC code rates (e.g., 4/15), achieving excellent error correction performance while maintaining manageable system complexity through systematic parameter selection.

The patent applies different permutation sequences to different bit groups based on their positions in the codeword. This local optimization approach allows each bit group to be treated with appropriate interleaving characteristics, improving overall error correction performance without requiring complete redesign of the entire interleaver structure, thus balancing performance and complexity.