LDPC Bit Interleaver Permutation for 256-Symbol Burst Error Spreading

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Solution Overview

Problem

Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation unless burst errors in digital broadcast channels are effectively distributed, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.

Innovation Solution

A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 3/15, using 256-symbol mapping, which interleaves the LDPC codeword on a bit group basis with a parallel factor of 360, employing a specific permutation order to distribute burst errors effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a bit interleaver is designed for BICM systems, then performance degradation from burst errors is prevented, but the design becomes complex and must be optimized for specific modulation orders and code parameters

Engineering Contradiction:

Improveperformance stabilityVSAvoidinterleaver design complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by designing the interleaver with specific parameters matched to the modulation order and code rate. The interleaver length is set to match the LDPC codeword length (64800 bits for rate 3/15), and the bit group size is set to 360 bits to align with the parallel processing factor. This parameter matching optimizes the interleaver for specific BICM configurations while maintaining reliability.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent segments the LDPC codeword into multiple bit groups, where each bit group contains a specific number of bits (e.g., 360 bits). The interleaver operates on these bit groups rather than individual bits, reducing the complexity of the interleaving operation while still effectively distributing burst errors across the modulated signal.

Inventive Principle:

Principle #1Segmentation

2Reliability

If the bit interleaver is optimized for specific code rate and modulation order, then error distribution is improved, but the adaptability to different broadcasting standards is reduced

Engineering Contradiction:

Improveerror distribution effectivenessVSAvoidbroadcasting standard compatibility

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent enables adaptability through parameter configuration. The interleaver is designed with configurable parameters including codeword length, code rate, modulation order, and bit group size. By changing these parameters, the same interleaver structure can be adapted to different broadcasting standards (e.g., DVB-T2, ATSC 3.0, 5G) while maintaining optimized error distribution performance for each specific configuration.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11018698B2Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 256-symbol mapping, and bit interleaving method using same

Publication Date: 2021.05.25 ELECTRONICS & TELECOMM RES INST

AI summary

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.