LDPC Decoding Pipeline Memory Index Switching for Trapping Recovery
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Solution Overview
Problem
Conventional bit-flipping LDPC decoders face errors due to delays in the decoding pipeline, leading to misjudgments and a higher error floor, as they often do not use the latest syndrome during decision-making, causing the decoder to enter a trapping status.
Innovation Solution
A memory controller and method for controlling data in a decoding pipeline that includes a memory-index control circuit and a decoder, which performs LDPC decoding in an initial phase, decoding phase, and output phase, using different orders to read codewords from the variable-node memory, allowing for syndrome calculation and bit-flipping algorithms to correct errors, thereby reducing pipeline delays and trapping status occurrences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit-flipping LDPC decoder uses a fixed decoding pipeline with a single data-index order, then the decoding structure is simple and easy to implement, but the decoder enters trapping status due to pipeline delays causing misjudgment of syndromes, resulting in higher error floors
Solution Approach 1:
The patent applies dynamics by making the data-index order changeable during decoding. The memory-index control circuit dynamically switches between first and second data-index orders based on whether the decoder has entered trapping status. This dynamic adaptation allows the system to escape trapping status by changing the access pattern to variable-node memory, thereby improving decoding reliability without requiring a completely complex pipeline structure.
Solution Approach 2:
The patent changes the parameter of data-index order used to access variable-node memory. By switching between different data-index orders (first order and second order), the system modifies how syndromes are calculated and applied. This parameter change allows the decoder to use different syndrome sequences, preventing misjudgment caused by pipeline delays and reducing the error floor.
2Speed
If the decoder uses the latest syndrome immediately in bit-flipping decisions, then decoding speed is fast, but pipeline delays cause the syndrome to be outdated by the time it reaches the variable-node unit, leading to misjudgment
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing multiple syndrome sequences in the syndrome memory before they are needed for decoding decisions. The syndrome calculation unit continuously generates syndromes and stores them in advance with different data-index orders. This allows the variable-node unit to access the correct, up-to-date syndrome without waiting for pipeline delays, maintaining both speed and accuracy.
Solution Approach 2:
The syndrome memory acts as an intermediary between the syndrome calculation unit and the variable-node unit. It buffers and manages multiple syndrome sequences, allowing the variable-node unit to retrieve the appropriate syndrome at the right time. This intermediary component decouples the timing between syndrome calculation and usage, eliminating the misjudgment problem caused by pipeline delays while maintaining fast decoding speed.
3Reliability
If multiple data-index orders are implemented to prevent trapping status, then decoding reliability improves, but the control circuit and memory access logic become more complex
Solution Approach 1:
The patent segments the syndrome storage and access into different data-index order modes. The syndrome memory is organized to store syndromes with different data-index orders separately, and the memory-index control circuit selectively accesses appropriate segments based on the current decoding state. This segmentation allows reliable error correction through multiple orders while keeping the control logic manageable by dividing the access patterns into distinct, controllable segments.
Solution Approach 2:
The system uses feedback from the syndrome check result to control the data-index order selection. When the syndrome check indicates trapping status, the feedback signal triggers a switch to the alternative data-index order. This feedback mechanism automates the selection process, improving reliability through adaptive order switching while minimizing control complexity by using simple conditional logic based on syndrome validation results.
Data Source
AI summary
A memory controller, for use in a data storage device, is provided. A low-density parity-check (LDPC) decoding procedure performed by the memory controller includes an initial phase, a decoding phase, and an output phase in sequence. The memory controller includes a memory-index control circuit and a decoder. The decoder includes a decoding pipeline to perform the decoding phase of the LDPC decoding procedure. After the data storage device is booted up, the decoder reads a plurality of first codewords from a variable-node memory using a first order via the memory-index control circuit for LDPC decoding. In response to the decoder determining that a specific codeword among the first codewords has decoding failure, the decoder is reset to read a plurality of second codewords from the variable-node memory using a second order via the memory-index control circuit for LDPC decoding. The first order is different from the second order.