LDPC Post-Processing Architecture for Trapping Set Error Floors
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Solution Overview
Problem
Low Density Parity Check (LDPC) codes suffer from an error floor issue, characterized by a reduction in the slope of the Bit Error Rate (BER) vs. channel Signal-to-Noise Ratio (SNR) curve at low BER levels, leading to higher bit error rates in wireless backhaul systems and other communication systems requiring extremely low error rates.
Innovation Solution
A post-processing algorithm and hardware system that injects noise of varying duration and magnitude over multiple iterations, and dynamically changes noise injection locations to resolve decoding errors caused by trapping sets, allowing the LDPC decoder to converge to a valid codeword.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If post-processing with single noise injection is used, then some trapping set errors are resolved, but many decoding errors remain unresolved due to limited error types handled
Solution Approach 1:
The patent segments the post-processing into multiple iterations, with each iteration handling different types of trapping set errors. The first iteration resolves errors of one type, the second iteration resolves errors of another type, and so on. This segmentation allows the system to progressively resolve multiple categories of decoding errors that a single noise injection cannot handle.
Solution Approach 2:
The patent implements periodic noise injection at regular intervals (multiple iterations) rather than a single continuous injection. Each periodic noise injection targets different error patterns, allowing the decoder to progressively converge from different local minima. This periodic action enables the system to handle diverse trapping set errors that require different perturbation timings.
2Ease of manufacture
If noise injection duration is fixed, then implementation is simple, but the decoder cannot effectively resolve different types of trapping set errors requiring different perturbation durations
Solution Approach 1:
The patent makes the noise injection duration dynamic by implementing multiple iterations with different duration settings. The first noise injection has a specific duration, and subsequent noise injections have different durations. This dynamic adjustment allows each iteration to effectively address different trapping set error characteristics, improving overall convergence while maintaining manageable implementation complexity through systematic duration variation.
3Loss of time
If single-shot noise injection is used, then latency is low, but the error floor reduction is insufficient for wireless backhaul requirements
Solution Approach 1:
The patent performs preliminary noise injections in multiple iterations before final decoding completion. Each preliminary noise injection prepares the decoder state for the next iteration, progressively eliminating different types of trapping set errors. This preliminary action across multiple iterations achieves superior error floor reduction compared to single-shot injection, while the total latency remains acceptable for wireless backhaul applications requiring BER below 10^-12.
Data Source
AI summary
Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.