LDPC Encoding Using Protograph Matrices Without Generator Storage
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Solution Overview
Problem
Conventional Low-Density Parity-Check (LDPC) codes are not hardware-friendly due to complex operations and substantial memory and circuitry requirements, making them difficult to implement in small circuits like system-on-a-chip, despite offering superior error correction and approaching theoretical maximum transmission rates.
Innovation Solution
A device and method for encoding data using LDPC codes that generates parity bits on-the-fly without constructing a generator matrix, utilizing a processor array and protograph matrices to perform LDPC coding operations, allowing for efficient encoding without storing a large generator matrix.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC codes are used to achieve superior error correction capabilities and approach theoretical maximum transmission rates, then error correction performance is improved, but hardware complexity and memory requirements increase substantially
Solution Approach 1:
The patent segments the LDPC encoding process into distinct functional modules: a processor array for parallel computation of parity bits, a memory subsystem for storing the H matrix, and control logic for coordinate generation. This segmentation allows each component to be optimized independently, reducing overall hardware complexity while maintaining error correction performance.
Solution Approach 2:
The patent introduces an intermediary coordinate generation mechanism that maps input data to appropriate parity check equations without requiring full generator matrix construction. This intermediary layer simplifies the encoding process by avoiding direct computation with large generator matrices, thereby reducing hardware complexity while preserving reliability.
2Reliability
If conventional LDPC codes are used to achieve superior error correction capabilities, then error correction performance is improved, but memory requirements increase substantially
Solution Approach 1:
The patent extracts only the essential H matrix from the conventional LDPC implementation, eliminating the need to store and process large generator matrices. By taking out only the necessary parity check information, the system achieves comparable error correction performance with significantly reduced memory requirements.
Solution Approach 2:
The patent changes the fundamental parameter from generator matrix representation to H matrix representation. This parameter change allows the system to compute parity bits on-demand using the sparser H matrix structure, dramatically reducing memory storage requirements while maintaining the ability to achieve superior error correction through iterative decoding.
3Productivity
If conventional LDPC codes are used to approach theoretical maximum transmission rates, then transmission efficiency is improved, but circuitry requirements increase substantially
Solution Approach 1:
The patent implements a dynamic encoding architecture where the processor array can be reconfigured for different code rates and block lengths. This dynamic capability allows the system to approach theoretical maximum transmission rates for various channel conditions without requiring separate dedicated circuitry for each configuration, thereby reducing overall circuitry requirements.
Solution Approach 2:
The patent creates a universal encoder design that can handle multiple LDPC code configurations through a single processor array implementation. By making the circuitry universal rather than specialized, the system achieves high transmission rates across different applications without proportionally increasing circuitry complexity.
Data Source
AI summary
A system and method is capable of performing a Low Density Parity Check (LDPC) coding operation on-the-fly without using a generator matrix. The system and method includes an input configured to receive data and an output configured to output a plurality of codewords. The system and method also includes a processor coupled between the input and the output. The processor is configured to encode the received data and produce the plurality of codewords using a plurality of parity bits. The processor creates the plurality of parity bits on-the-fly using a portion of an LDPC matrix and a protograph matrix.