LDPC Decoder Q/P Message Update for Lower Routing Complexity
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Solution Overview
Problem
Existing low density parity check (LDPC) decoders face complexities in interconnect issues and require significant computational resources, limiting their efficiency and scalability in error correction for next-generation communication and data storage systems.
Innovation Solution
The development of novel techniques for decoding LDPC codes, including the use of check node units (CNUs) with comparators for minimizing message storage and routing logic, and the application of log-likelihood ratios (LLRs) in a layered decoding architecture with cyclic shifts, reduces computational complexity and enhances parallel processing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC decoder designs are used, then error correction capability is achieved, but device complexity and interconnect issues increase
Solution Approach 1:
The decoder is divided into multiple independent check node unit arrays, where each array processes a specific block row of the LDPC parity check matrix. This segmentation reduces interconnect complexity by localizing processing within each array while maintaining error correction capability through coordinated operation of multiple arrays.
Solution Approach 2:
The patent introduces a layered architecture where check node units are organized in multiple arrays processing different block rows simultaneously. This dimensional organization transforms the decoder structure from a flat complex interconnect to a multi-layered architecture with reduced inter-array communication requirements.
2Productivity
If more computational resources are allocated to LDPC decoding, then decoding performance improves, but device complexity and resource requirements increase
Solution Approach 1:
Computational tasks are segmented across multiple check node unit arrays, with each array handling specific block rows. This distribution maintains high decoding performance through parallel processing while reducing the computational burden on individual units and simplifying overall device complexity.
Solution Approach 2:
Each check node unit array performs partial processing of the overall decoding task, focusing on specific block rows. This partial action approach allows the system to achieve high decoding performance through cumulative results from multiple arrays without requiring each individual array to handle the full computational load.
3Device complexity
If message storage and routing logic are reduced, then device complexity decreases, but decoding accuracy may be compromised
Solution Approach 1:
Message processing is segmented within each check node unit array, handling specific block rows independently. This localization reduces message storage and routing logic complexity while maintaining decoding accuracy through proper coordination between arrays and preservation of essential message information.
Solution Approach 2:
Each check node unit array is designed with specialized local processing capabilities optimized for its specific block row processing. This local quality approach reduces the need for complex global message routing while ensuring decoding accuracy through locally optimized processing within each array.
Data Source
AI summary
A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.