LDPC Transmission Coding Rate Adaptation With Lower Circuit Scale
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Solution Overview
Problem
Existing erasure correction codes face challenges in efficiently changing coding rates in response to varying communication quality, leading to increased circuit scales for encoders and decoders, which hinders transmission efficiency and erasure correction capability.
Innovation Solution
The method generates a low-density parity check convolutional code (LDPC-CC) with a coding rate of 1/3 by modifying parity check polynomials and inserting known information to adjust the coding rate, reducing the circuit scales of encoders and decoders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the Reed-Solomon code block length is increased to improve correction capability, then the erasure correction capability is improved, but the amount of computation and circuit scale increase
Solution Approach 1:
The patent changes the fundamental parameter of the error correction code from Reed-Solomon to LDPC code, which has different structural characteristics. LDPC codes use a sparse parity-check matrix that enables efficient decoding algorithms with lower computational complexity and smaller circuit implementation, while maintaining or improving erasure correction capability compared to Reed-Solomon codes of comparable length
2Adaptability or versatility
If multiple erasure correction codes with different coding rates are prepared to adapt to varying communication quality, then the adaptability is improved, but the device complexity increases
Solution Approach 1:
The patent introduces dynamic adaptability by enabling the LDPC code to flexibly adjust its coding rate based on communication conditions. This is achieved through configurable parameters in the parity-check matrix and decoding algorithm that allow the same hardware implementation to operate at different coding rates (e.g., 1/2, 2/3, 3/4) without requiring multiple separate code structures, thus maintaining adaptability while controlling device complexity
Data Source
AI summary
A transmission apparatus includes a signal processing circuit configured to obtain information data bits to be transmitted; add known information data bits to the information data bits to generate first data blocks; perform error-correction coding on the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate; remove the known information data bits from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate; and modulate the second coded data blocks using a modulation scheme to generate a modulated signal, which is then transmitted. A number of the known information data bits depends on a number of the information data bits such that the first code rate is fixed regardless of the number of the information data bits.