LDPC Rate-Compatible Parity Check Matrix with Row Orthogonality

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Solution Overview

Problem

Current wireless communication systems face challenges in efficiently encoding and decoding data at high rates, particularly in low-density parity-check (LDPC) codes, which are essential for emerging technologies like 5G New Radio (NR), due to issues with error correction and data transmission reliability.

Innovation Solution

The implementation of a method and apparatus for LDPC decoding using a parity check matrix with row orthogonality, specifically designed for lifted LDPC codes, which enhances the decoding process by ensuring that each pair of consecutive rows connected to punctured variable nodes maintains orthogonality, thereby improving decoding efficiency and reducing processing delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If LDPC decoding is performed using conventional parity check matrices, then decoding can be implemented, but processing delays increase and decoding efficiency decreases

Engineering Contradiction:
Improvedecoding speedVSAvoidprocessing delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies parameter changes by modifying the structure of the parity check matrix to achieve row orthogonality. Specifically, the patent transforms the conventional parity check matrix into one where rows are orthogonal, which changes the mathematical properties of the matrix to enable more efficient decoding operations and reduce processing delays in LDPC decoding

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies local quality by ensuring that specific rows in the parity check matrix (those connected to punctured variable nodes) have orthogonal properties, while other rows maintain their conventional structure. This localized application of orthogonality optimizes the decoding process for critical paths without requiring complete restructuring of the entire matrix

Inventive Principle:
Principle #3Local quality

2Reliability

If row orthogonality is implemented in the parity check matrix, then decoding efficiency and reliability improve, but matrix structure complexity increases

Engineering Contradiction:
Improveerror correction reliabilityVSAvoidmatrix structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the structural parameters of the parity check matrix by imposing row orthogonality constraints. This parameter change improves the mathematical properties of the matrix, leading to better error correction reliability and more stable decoding convergence, while the complexity increase is managed through systematic construction methods

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If conventional LDPC coding is used for rate compatible design, then implementation is straightforward, but processing delays increase and updated variable node sums are less available

Engineering Contradiction:
Improveimplementation easeVSAvoidprocessing delay
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent modifies the LDPC code structure by implementing row orthogonality in the parity check matrix, which changes the computational characteristics of the decoding process. This parameter change reduces processing delays and improves the availability of updated variable node sums during iterative decoding, while maintaining rate compatibility

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies segmentation by dividing the parity check matrix into distinct rows with orthogonal properties, particularly for rows connected to punctured variable nodes. This segmentation allows the decoder to process orthogonal rows more efficiently, reducing overall processing delay and improving the timing of variable node sum updates

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11411581B2Row orthogonality in LDPC rate compatible design
Publication Date: 2022.08.09 QUALCOMM INC
  • US11411581B2 patent drawing
  • US11411581B2 patent drawing
  • US11411581B2 patent drawing

AI summary

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low-density parity check (LDPC) codes, for example, using a parity check matrix having full row-orthogonality. An exemplary method for performing low-density parity-check (LDPC) decoding includes receiving soft bits associated to an LDPC codeword and performing LDPC decoding of the soft bits using a parity check matrix, wherein each row of the parity check matrix corresponds to a lifted parity check of a lifted LDPC code, at least two columns of the parity check matrix correspond to punctured variable nodes of the lifted LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which the at least two punctured variable nodes are both connected.