LDPC Rate Matching and Interleaving for Stable Retransmission
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Solution Overview
Problem
Existing methods for selecting starting bits and rate matching in quasi-cyclic LDPC coding systems lead to unstable data retransmission performance, particularly in high order modulation and fading channels, with existing technologies failing to effectively address these issues.
Innovation Solution
A method for selecting starting bit locations based on redundancy versions and employing bit interleaving, specifically using a block interleaver with column permutations, to improve transmission performance and stability in LDPC coded data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing methods for selecting starting bits and rate matching are used in quasi-cyclic LDPC coding systems, then the system can achieve basic transmission functionality, but the retransmission performance becomes unstable, particularly in high order modulation and fading channels
Solution Approach 1:
The patent applies dynamics by making the starting bit selection adaptive to different transmission scenarios. Specifically, different starting bit positions are selected based on the redundancy version index, allowing the system to dynamically adjust to varying channel conditions and modulation orders. This dynamic adaptation resolves the contradiction by enabling stable retransmission performance across diverse fading channels and high order modulation schemes.
Solution Approach 2:
The patent changes the parameter of starting bit position based on the redundancy version index. By systematically varying the starting bit position according to the redundancy version, the patent ensures that retransmitted data packets have optimized performance characteristics. This parameter change strategy directly addresses the instability issue in existing methods while maintaining compatibility with standard LDPC coding structures.
2Productivity
If rate matching is performed by selecting bits from a cache storing LDPC codewords according to a redundancy version, then the transmission rate can be adjusted to match allocated resources, but the selection of starting bit location significantly impacts system performance and causes instability in retransmission
Solution Approach 1:
The patent applies preliminary action by pre-defining the relationship between redundancy version indices and starting bit positions. This predetermined mapping allows the rate matching process to efficiently select appropriate starting bits without complex real-time calculations. The preliminary establishment of this mapping resolves the contradiction by enabling both flexible rate adaptation and stable retransmission performance through systematic bit selection.
3Device complexity
If quasi-cyclic LDPC coding is used to achieve low complexity and good AWGN channel performance, then the codec complexity is reduced, but the performance deteriorates in fading channels and high order modulation scenarios
Solution Approach 1:
The patent applies local quality by optimizing specific aspects of the transmission process (starting bit selection and interleaving) without changing the overall quasi-cyclic LDPC coding structure. This localized optimization maintains the low complexity advantage of quasi-cyclic LDPC while improving performance in fading channels and high order modulation scenarios through targeted enhancements in the rate matching and interleaving stages.
Data Source
AI summary
Methods and Apparatus for processing data encoded by low density parity check (LDPC) in a communication system are disclosed herein. In one embodiment, a method performed by a first node is disclosed. The method comprises: encoding an information bit sequence based on an LDPC coding scheme to obtain an encoded bit sequence; generating a master bit sequence based on the encoded bit sequence; selecting a subset of the master bit sequence according to a rate matching rule to obtain a rate matched bit sequence; interleaving the rate matched bit sequence according to a predetermined index sequence to obtain a to-be-transmitted bit sequence; and transmitting the to-be-transmitted bit sequence to a second node.