Erasure LDPC Rate Matching for Multi-Slot UCI Multiplexing

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Solution Overview

Problem

Current wireless communication systems, particularly in 5G NR, face challenges in efficiently managing rate matching for transport blocks (TBs) across multiple slots, especially when uplink control information (UCI) multiplexing occurs, leading to inefficient resource allocation and dynamic update issues.

Innovation Solution

The method involves calculating slot lengths for each uplink slot based on rate matching output bits, allocating bits for modulation, and skipping bits for UCI multiplexing, allowing for efficient resource management and dynamic UCI multiplexing support by determining slot boundaries and refraining from allocating bits for UCI in the rate matching process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If rate matching is performed for TB across multiple slots with dynamic UCI multiplexing, then resource utilization and communication efficiency are improved, but the complexity of managing rate matching output bit allocation and slot boundary determination increases

Engineering Contradiction:
Improveresource utilizationVSAvoidrate matching management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the rate matching process by introducing slot boundary determinations that divide the multi-slot transmission into manageable segments. Each slot boundary acts as a segmentation point that allows independent rate matching calculations for different slot groups, reducing the overall complexity while maintaining resource utilization benefits across multiple slots.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by determining slot boundaries and calculating rate matching output bit allocations before the actual transmission occurs. This advance planning allows the system to pre-configure the rate matching parameters for each slot, eliminating the need for complex dynamic adjustments during transmission and reducing real-time processing complexity.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If bits are skipped for UCI multiplexing in the rate matching process, then dynamic UCI multiplexing is supported, but the allocation of rate matching output bits becomes more complex

Engineering Contradiction:
Improvedynamic UCI multiplexing supportVSAvoidbit allocation complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamics by making the rate matching process adaptive to UCI multiplexing requirements. The system dynamically adjusts the bit allocation by skipping appropriate bits when UCI multiplexing is detected, allowing flexible support for different UCI scenarios while maintaining a systematic approach through slot boundary-based segmentation that prevents excessive complexity.

Inventive Principle:
Principle #15Dynamics

3Manufacturing precision

If slot length is calculated for each UL slot based on rate matching output bits, then precise resource allocation is achieved, but the calculation and management overhead increases

Engineering Contradiction:
Improveresource allocation precisionVSAvoidcalculation overhead
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent reduces calculation overhead by segmenting the slot length calculation into slot boundary-based units. Instead of calculating for every individual slot independently, the system determines slot boundaries once and uses them as reference points for rate matching output bit allocation, maintaining precision while reducing redundant calculations across the multi-slot transmission.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250096933A1Erasure style LDPC rate matching for TB over multiple slots
Publication Date: 2025.03.20 QUALCOMM INC
  • US20250096933A1 patent drawing
  • US20250096933A1 patent drawing
  • US20250096933A1 patent drawing

AI summary

Methods, apparatuses, and computer-readable storage medium for rate matching for TBoMS are provided. An example method includes calculating a slot length for each UL slot of a plurality of UL slots, the slot length for each UL slot being associated with a plurality of rate matching output bits, each UL slot including a starting point for the plurality of rate matching output bits, the slot length for each UL slot being associated with a starting boundary, the plurality of UL slots being associated with at least one of a single TB or a single rate matching. The example method may include allocating one or more bits of the plurality of rate matching output bits for a modulation process. The example method may include refraining allocating at least one bit of the plurality of rate matching output bits for the modulation process, the at least one bit corresponding to UCI multiplexing.