LDPC Receiver Decoding Using Segmented Parity Check Matrices

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Solution Overview

Problem

Existing receivers processing superposition-coded signals face increased decoding times for the upper layer signal, which in turn prolong the processing time for the base layer signal, necessitating a method to reduce decoding time while maintaining low error probability.

Innovation Solution

A receiver is designed to decode the upper layer signal using a part of the parity check matrix, specifically employing Low Density Parity Check (LDPC) information word bits and parity bits, and encoding these to generate additional parity bits, allowing for efficient decoding and reconstruction of both layer signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the receiver uses the entire parity check matrix to decode the upper layer signal, then the decoding accuracy is improved, but the decoding time increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoiddecoding time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The parity check matrix is divided into multiple sub-matrices, and decoding is performed sequentially using different sub-matrices at different stages. This segmentation allows the system to achieve both fast initial decoding and accurate final decoding, resolving the contradiction between speed and accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A preliminary decoding step is performed using a first sub-matrix before the final decoding step using a second sub-matrix. This preliminary action provides a quick initial result that can be refined later, reducing overall decoding time while maintaining accuracy.

Inventive Principle:
Principle #10Preliminary action

2Stability of the object's composition

If the receiver processes the upper layer signal completely before processing the base layer signal, then the superposition coding structure is maintained, but the overall processing time increases

Engineering Contradiction:
Improvesuperposition coding structureVSAvoidsignal processing speed
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

The decoding process is segmented into multiple stages with different sub-matrices, allowing parallel processing opportunities and optimizing the overall processing pipeline while maintaining the superposition coding structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically adjusts which sub-matrix is used at each decoding stage, enabling flexible resource allocation and optimized processing speed while preserving the structural integrity of the superposition coded signal.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10833804B2Receiver and method for processing a signal thereof
Publication Date: 2020.11.10 SAMSUNG ELECTRONICS CO LTD
  • US10833804B2 patent drawing
  • US10833804B2 patent drawing
  • US10833804B2 patent drawing

AI summary

A receiver is provided. The receiver includes: a first decoder configured to decode a superposition-coded signal by using a parity check matrix to generate Low Density Parity Check (LDPC) information word bits and first parity bits corresponding to a first layer signal; an encoder configured to encode the LDPC information word bits and the first parity bits to generate second parity bits, or encode the LDPC information word bits to generate the first parity bits and the second parity bits, by using the parity check matrix; and a second decoder configured to decode a signal which is generated by removing the first layer signal, corresponding to the LDPC information word bits, the first parity bits, and the second parity bits, from the superposition-coded signal, to reconstruct bits transmitted through the second layer signal.