LDPC Receiver Parallel Parity-Check Updates for Faster Decoding
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Solution Overview
Problem
Low-Density Parity-Check (LDPC) codes used in 5G NR communication networks face challenges in processing time and hardware requirements due to sequential updating of parity checks, leading to increased processing time and hardware size, as well as synchronization issues in parallel updates.
Innovation Solution
A method for accelerating bit error correction by updating soft bit values in parallel using grouped rows of the parity-check matrix, allowing for simultaneous updating of non-overlapping or overlapping rows, and computing shared and new check-to-bit values to reduce processing time and hardware needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If sequential updating of parity checks is used, then processing time is reduced, but hardware size increases
Solution Approach 1:
The parity-check matrix rows are segmented into multiple groups, where each group can be processed independently in parallel. This segmentation allows the system to divide the overall parity check updating task into smaller, concurrent sub-tasks, reducing total processing time while maintaining manageable hardware requirements for each processing unit.
Solution Approach 2:
The patent introduces a new dimension of parallelization by processing multiple rows simultaneously across different processing units. Instead of sequential single-row processing, the system operates in a multi-dimensional parallel space where multiple row updates occur concurrently, achieving faster processing without proportionally increasing hardware size.
2Loss of time
If parallel updating of all rows is used, then processing time is reduced, but hardware size increases
Solution Approach 1:
The parity-check matrix rows are segmented into multiple groups, where each group can be processed independently in parallel. This segmentation allows the system to divide the overall parity check updating task into smaller, concurrent sub-tasks, reducing total processing time while maintaining manageable hardware requirements for each processing unit.
3Loss of time
If parallel updating of overlapping rows is used, then processing time is reduced, but synchronization complexity increases
Solution Approach 1:
The patent introduces intermediary data structures and coordination mechanisms that manage the parallel updating of overlapping rows. These intermediaries handle the synchronization requirements by coordinating updates across processing units, reducing race conditions and conflicts while maintaining the benefits of parallel processing.
Solution Approach 2:
The system implements feedback mechanisms where processing units communicate update status and coordinate their operations. This feedback loop allows overlapping row updates to be synchronized efficiently, with processing units adjusting their operations based on the state of shared data, thereby reducing synchronization complexity.
Data Source
AI summary
A method for accelerating bit error correction in a receiver in a radio communication network, wherein the receiver is configured to update soft bit values associated with each code bit of a block code based on parallel parity checks. The method includes receiving a block code encoded message, and for any group of two or more rows of a parity-check matrix of the block code: when the two or more rows are non-overlapping: combining the two or more rows in a row group for parallel updating, updating, in parallel, the parity checks of the row group for the received message, and forming a message estimate based on the updated parity checks. Corresponding computer program product, apparatus, and receiver are also disclosed.