LDPC Receiver Decoding for Superposition-Coded Signals

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Solution Overview

Problem

Existing receivers processing superposition-coded signals face inefficiencies due to longer decoding times for upper layer signals, which in turn prolong the processing time for base layer signals, necessitating a method to reduce decoding time while maintaining low error probability.

Innovation Solution

A receiver is designed to decode upper layer signals using a part of the parity check matrix, specifically employing Low Density Parity Check (LDPC) information word bits and parity bits, and encoding these to generate additional parity bits, allowing for efficient decoding and reconstruction of both layer signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the receiver decodes the upper layer signal using the entire parity check matrix to ensure low error probability, then the decoding reliability is improved, but the decoding time increases

Engineering Contradiction:
Improvedecoding reliabilityVSAvoiddecoding time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The parity check matrix is divided into multiple sub-matrices, and the decoding process is segmented into multiple stages. In the first stage, a first sub-matrix is used for initial decoding to quickly obtain the upper layer signal. In the second stage, additional sub-matrices are used to further reduce errors. This segmentation allows the system to achieve low error probability while significantly reducing decoding time compared to using the entire matrix in one stage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The receiver performs preliminary decoding of the upper layer signal using a portion of the parity check matrix before fully decoding the base layer signal. This preliminary action enables the system to quickly process the upper layer and remove its contribution from the superposition-coded signal, thereby reducing the overall processing time while maintaining acceptable error rates through subsequent refinement stages.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If the receiver processes the upper layer signal completely before processing the base layer signal, then the decoding accuracy is improved, but the overall processing productivity decreases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidsignal processing productivity
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The decoding process is segmented into parallel stages: while the first decoder is processing the upper layer signal using the first sub-matrix, the second decoder simultaneously begins processing the base layer signal using the second sub-matrix. This segmentation enables parallel processing that maintains decoding accuracy through multi-stage verification while significantly improving overall processing productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The receiver maintains continuous useful action by overlapping the decoding operations of both layers. The first decoder continues refining the upper layer signal while the second decoder simultaneously processes the base layer signal. This continuous parallel processing eliminates idle waiting time and improves productivity without sacrificing decoding accuracy, as both decoders operate concurrently rather than sequentially.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS11838124B2Receiver and method for processing a signal thereof
Publication Date: 2023.12.05 SAMSUNG ELECTRONICS CO LTD
  • US11838124B2 patent drawing
  • US11838124B2 patent drawing
  • US11838124B2 patent drawing

AI summary

A receiver is provided. The receiver includes: a first decoder configured to decode a superposition-coded signal by using a parity check matrix to generate Low Density Parity Check (LDPC) information word bits and first parity bits corresponding to a first layer signal; an encoder configured to encode the LDPC information word bits and the first parity bits to generate second parity bits, or encode the LDPC information word bits to generate the first parity bits and the second parity bits, by using the parity check matrix; and a second decoder configured to decode a signal which is generated by removing the first layer signal, corresponding to the LDPC information word bits, the first parity bits, and the second parity bits, from the superposition-coded signal, to reconstruct bits transmitted through the second layer signal.