LDPC Receiver Decoding for Superposition-Coded Signal Layers

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Solution Overview

Problem

Existing receivers processing superposition-coded signals face increased decoding times for the upper layer signal, which in turn prolong the processing time for the base layer signal, necessitating a method to reduce the decoding time of the upper layer signal with low error probability.

Innovation Solution

A receiver is designed to decode the upper layer signal using a part of the parity check matrix, generating Low Density Parity Check (LDPC) information word bits and parity bits, and encoding these to reduce decoding complexity and time, while reconstructing bits transmitted through the second layer signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the receiver uses the entire parity check matrix to decode the upper layer signal, then the decoding accuracy is improved, but the decoding time increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoiddecoding time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The parity check matrix is divided into multiple sub-matrices, and the decoding process is segmented into multiple stages. In the first stage, a first sub-matrix is used for initial decoding to obtain preliminary decoding results. In the second stage, a second sub-matrix is used to further process and correct errors in the preliminary results. This segmentation allows the system to achieve high decoding accuracy without requiring the entire parity check matrix to be processed at once, thereby reducing the overall decoding time while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the receiver processes the upper layer signal completely before processing the base layer signal, then the error probability of the upper layer is reduced, but the overall processing time increases

Engineering Contradiction:
Improveerror probabilityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The receiver performs preliminary decoding of the upper layer signal using a first sub-matrix to obtain preliminary decoding results before complete processing is finished. This allows the base layer signal processing to begin earlier based on these preliminary results, rather than waiting for the entire upper layer decoding to complete. The preliminary action reduces the overall processing time while maintaining adequate error probability performance through subsequent refinement stages.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the receiver uses more iterations in the decoding process, then the decoding accuracy is improved, but the processing complexity increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The decoding process is divided into multiple stages, each using different sub-matrices of the parity check matrix. The first stage uses a first sub-matrix for initial decoding with a limited number of iterations. The second stage uses a second sub-matrix for further error correction with additional iterations only when needed. This segmented approach achieves high decoding accuracy without requiring the full complexity of processing the entire parity check matrix with maximum iterations throughout, thereby reducing overall processing complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11349605B2Receiver and method for processing a signal thereof
Publication Date: 2022.05.31 SAMSUNG ELECTRONICS CO LTD
  • US11349605B2 patent drawing
  • US11349605B2 patent drawing
  • US11349605B2 patent drawing

AI summary

A receiver is provided. The receiver includes: a first decoder configured to decode a superposition-coded signal by using a parity check matrix to generate Low Density Parity Check (LDPC) information word bits and first parity bits corresponding to a first layer signal; an encoder configured to encode the LDPC information word bits and the first parity bits to generate second parity bits, or encode the LDPC information word bits to generate the first parity bits and the second parity bits, by using the parity check matrix; and a second decoder configured to decode a signal which is generated by removing the first layer signal, corresponding to the LDPC information word bits, the first parity bits, and the second parity bits, from the superposition-coded signal, to reconstruct bits transmitted through the second layer signal.