5G NR LDPC Interleaving in Registers for Faster Rate Matching
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Solution Overview
Problem
Current signal processing techniques for 5G NR are inefficient due to the need for modulo operations and sequential processing in rate matching and de-interleaving, which are not optimized for the shorter slot times of 5G NR, leading to increased processing cycles and reduced performance.
Innovation Solution
Implement parallel processing methods within processor registers for de-interleaving and rate de-matching, eliminating the need for modulo operations and allowing bulk memory operations, thereby reducing CPU cycles and improving processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sequential processing with modulo operations is used for rate matching and de-interleaving, then processing accuracy is maintained, but processing speed decreases and CPU cycles increase
Solution Approach 1:
The patent replaces the traditional sequential software-based processing with a parallel hardware implementation using Multiple cyclic buffers and Multiple rate matching units. This substitution of mechanical processing architecture eliminates the need for complex modulo operations and enables simultaneous processing of multiple code blocks, achieving up to 40 times faster processing speed while maintaining processing accuracy.
Solution Approach 2:
The patent divides the rate matching and de-interleaving processing into multiple independent units operating in parallel. Each rate matching unit processes a specific code block independently using its own cyclic buffer, allowing simultaneous execution of multiple processing tasks. This segmentation transforms the sequential complex algorithm into multiple simpler parallel operations.
2Productivity
If parallel processing is implemented for de-interleaving and rate de-matching, then processing speed increases significantly, but implementation complexity increases
Solution Approach 1:
The patent designs rate matching units and cyclic buffers that can handle multiple code blocks with different parameters simultaneously. Each unit is configured to process various code block sizes, modulation schemes, and redundancy versions through universal processing logic, reducing the overall implementation complexity despite the parallel architecture.
Solution Approach 2:
The patent creates multiple identical rate matching unit templates that can be instantiated in parallel. Instead of designing complex unique processing logic for each processing channel, the same standardized unit is copied and configured for different code blocks, simplifying the implementation of parallel processing while maintaining high productivity.
3Duration of action of moving object
If traditional rate matching with modulo operations is used, then processing accuracy is ensured, but processing time increases beyond 5G NR slot time requirements
Solution Approach 1:
The patent pre-allocates multiple cyclic buffers and configures rate matching units before processing begins. The parallel processing architecture is established in advance, allowing immediate simultaneous processing of multiple code blocks without sequential delays. This preliminary setup ensures that processing completes within the strict 5G NR slot time while maintaining reliability through redundant parallel processing paths.
Data Source
AI summary
Apparatuses and methods are disclosed for a communication device associated with a wireless transmission. In one embodiment, a method includes performing one of a low-density parity check, LDPC, decoding process and an LDPC encoding process by loading a set of bits, in parallel, into a plurality of registers, the set of bits being distributed among the plurality of registers; one of de-interleaving and interleaving the loaded set of bits within the plurality of registers by rearranging the loaded set of bits into one of a de-interleaved and an interleaved set of bits; and after the set of bits is rearranged into the one of the de-interleaved and the interleaved set of bits within the plurality of registers, writing the one of the de-interleaved and the interleaved set of bits, in parallel, from the plurality of registers to memory.