LDPC Decoder Reliability Quantization for Limited Bit-Length Storage
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Solution Overview
Problem
Existing LDPC code decoders face challenges in recording large reliability values due to limited bit length in actual circuit implementations, as the number of iterations is predetermined and not suited to varying operating conditions.
Innovation Solution
A parity-check-code decoder with a recording controller that dynamically adjusts bit lengths based on reliability values by dividing the parity-check-code matrix into column groups with shared column weights, using a separator, quantizing determiner, and quantizer to output characterizing signals with appropriate bit lengths, and determines shift signals to prevent saturation and optimize memory storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of iterations is increased to improve decoding accuracy, then the reliability values become larger, but the bit length required for recording increases beyond circuit implementation limits
Solution Approach 1:
The patent applies dynamic adjustment of bit lengths for recording reliability values based on the magnitude of the values. The system dynamically determines appropriate bit lengths during the decoding process, allowing flexible adaptation to varying reliability value ranges without requiring a fixed large bit length for all cases.
Solution Approach 2:
The patent changes the parameter of bit length according to the magnitude of reliability values. By adjusting the bit length parameter dynamically based on the actual value range encountered during iterations, the system can accommodate larger reliability values from increased iterations without permanently requiring larger storage capacity.
2Device complexity
If a fixed predetermined number of iterations is used, then the decoding process is simplified, but the system cannot adapt to varying operating conditions and channel qualities
Solution Approach 1:
The patent introduces dynamic adaptation mechanisms that allow the decoding process to adjust to varying operating conditions. The system can modify its operation based on channel quality and other factors while maintaining a structured iterative approach, balancing simplicity with adaptability.
Data Source
AI summary
A parity-check-code decoder includes: a verifying device that multiplies (N) bit nodes by a matrix provided with (N) columns so as to obtain a plurality of check nodes; a reliability generator that generates a reliability index for each of the bit nodes in accordance with a channel; a reliability-updating device that uses the bit nodes and the check nodes to exchange message iteratively, and following each iteration, updates (N) exchange results corresponding to the (N) columns; and a recording controller that includes a separator, a quantizing determiner and a quantizer. The separator divides the matrix into at least one column group based on the characterizing signals. The quantizing determiner determines a shift signal for each column group based on the characterizing signals. The quantizer quantizes the characterizing signals according to the shift signals for subsequent output.