LDPC Rotator Circuit for Stall-Free Cyclic LLR Rotation
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Solution Overview
Problem
Conventional LDPC decoder implementations face inefficiencies in implementing an LDPC rotator circuit due to the need for different cyclic rotations applied to LLRs from each block column, leading to stalling and reduced throughput in communication devices.
Innovation Solution
A low-density parity check (LDPC) rotator circuit with a parallelism of at least two, utilizing a series of operations that includes shifting and combining circuits, and registers to manage padding values, allowing for efficient rotation functions without stalling, thereby improving latency and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If different cyclic rotations are applied to LLRs from each block column in conventional LDPC decoder implementations, then the rotation function can be performed, but stalling occurs and throughput is reduced
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing rotation values in a rotation value storage unit before the actual rotation operation. The rotation value generation unit computes rotation values based on the base graph and lifting factor, and these pre-computed values are stored for immediate retrieval during the rotation function, eliminating the need for real-time computation and preventing stalling.
Solution Approach 2:
The patent implements dynamics by making the rotation values configurable and adaptable to different base graphs and lifting factors. The rotation value generation unit can dynamically generate different rotation values based on the specific LDPC code configuration, allowing the system to adapt to various coding schemes without hardware redesign, thus maintaining high throughput across different standards.
2Productivity
If conventional LDPC rotator circuit implementations are used, then rotation functions can be performed, but the circuit complexity increases and efficiency decreases
Solution Approach 1:
The patent segments the rotator circuit into distinct functional units: a rotation value generation unit that computes rotation values, a rotation value storage unit that holds pre-computed values, and a rotation execution unit that applies the rotation. This segmentation allows each unit to be optimized independently and simplifies the overall control logic, reducing circuit complexity while maintaining efficiency.
Solution Approach 2:
The patent replaces complex mechanical rotation operations with a lookup-based system. Instead of implementing complex cyclic shift circuits that would require numerous flip-flops and control logic, the system uses a storage unit to hold pre-computed rotation values and a simple retrieval mechanism to apply the appropriate rotation, significantly reducing circuit complexity.
Data Source
AI summary
A communication device comprises a low density parity check, LDPC, rotator circuit comprising sets of registers and configured to have a parallelism, P, of at least two, and to rotate a data sequence of Z data values by R positions, wherein ceil (Z/P) input blocks of P input values is accepted during a first subset of operations, which, before completion, ceil (Z/P) output blocks are provided during a second subset of operations. A padded input block is provided by mod (Z,P) of Z data values and P-mod (Z,P) of padding values when Z is not a multiple of P. The second register set is written with registered values derived before the second subset of operations begins and the values are not overwritten before the padded input block is accepted, and a P output value in an output block is a function of a registered value in the second register set.