LDPC Decoder Rotator Sharing for Lower Hardware and Latency
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Solution Overview
Problem
Conventional LDPC decoder implementations for the 3GPP New Radio LDPC code require significant hardware resources and result in high latency due to the need for numerous rotators, core variable node memories, and check node processor ports, as well as a large number of decoding operations, especially when processing basegraphs with a high number of rows.
Innovation Solution
The proposed solution involves an LDPC decoder design with reduced hardware requirements and processing operations by optimizing the number of rotators, core variable node memories, and check node processor ports, and by grouping LDPC decoding operations into fewer sub-steps, allowing for efficient processing of basegraphs with fewer active components and reduced interconnection complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC decoder implementations use numerous rotators, core variable node memories, and check node processor ports to process basegraphs with high number of rows, then decoding accuracy is maintained, but hardware resource requirements and device complexity increase significantly
Solution Approach 1:
The patent segments the basegraph processing by dividing it into multiple base graph units, where each unit can be processed independently or in parallel. This segmentation allows the decoder to handle large basegraphs without requiring all hardware resources simultaneously, thus reducing peak hardware requirements while maintaining decoding accuracy through systematic processing of divided units.
Solution Approach 2:
The patent implements dynamic resource allocation where the number of active rotators, memories, and processor ports is adjusted based on the current processing stage and requirements. This dynamic approach allows the system to use minimal resources for simple operations while scaling up resources only when necessary for complex processing tasks, optimizing the balance between accuracy and hardware complexity.
2Reliability
If conventional LDPC decoder implementations process basegraphs with high number of rows using traditional methods, then complete decoding is achieved, but latency and processing time increase
Solution Approach 1:
By dividing the basegraph into multiple smaller base graph units, the patent enables parallel processing of these units through multiple decoding operations. This segmentation transforms a single long processing sequence into multiple shorter parallel sequences, significantly reducing overall latency while ensuring complete decoding through systematic processing of all units.
Solution Approach 2:
The patent maintains continuous decoding operations by overlapping the processing of different base graph units. While one unit is being decoded, preparation for the next unit can begin, and results from completed units can be immediately used. This continuous action eliminates idle time between processing stages, reducing total latency while ensuring complete decoding.
3Device complexity
If the number of rotators and check node processor ports is reduced in LDPC decoder design, then hardware resource requirements and interconnection complexity decrease, but the number of required decoding operations increases
Solution Approach 1:
The patent compensates for reduced hardware resources by segmenting the basegraph into multiple units that can be processed sequentially or in smaller parallel groups. This segmentation distributes the total number of decoding operations across multiple smaller tasks, allowing the use of fewer rotators and processor ports while still achieving complete decoding through systematic processing of all segments.
Solution Approach 2:
The patent employs periodic processing patterns where decoding operations are performed in structured cycles across different base graph units. This periodic action allows the limited number of rotators and processor ports to be reused efficiently across multiple processing stages, reducing the need for large numbers of simultaneous resources while maintaining overall decoding throughput through systematic repetition of processing cycles.
Data Source
AI summary
An electronic device is described that is configured to perform a series of low density parity check, LDPC, decoding operations that use at least one basegraph that comprises two or more columns, each column associated with a set of two or more soft bit values. The electronic device includes two or more rotators, each rotator configured to rotate an order of a subset of two or more soft bit values of the set of two or more soft bit values of a column when activated in an LDPC decoding operation; and wherein rotations associated with each column in each basegraph are performed by a particular one of the rotators of the two or more rotators, wherein each rotator performs rotations for a set of one or more columns, with at least one of the rotators performing rotations for two or more columns in a same basegraph.