Layered LDPC Decoding with Parallel Row-Group Bit Correction
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Solution Overview
Problem
The existing methods for bit error correction in LDPC codes in 5G NR communication networks face challenges such as increased processing time, hardware size, and synchronization issues due to sequential or parallel updating of parity checks, which can lead to race conditions and more iterations.
Innovation Solution
Implementing a method that groups rows of the parity-check matrix for parallel updating, allowing for simultaneous processing of non-overlapping or overlapping rows, reducing the need for synchronization and enabling more efficient parallelization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If sequential updating of parity checks is used, then processing time increases, but hardware size is reduced
Solution Approach 1:
The parity-check matrix rows are segmented into multiple groups, where each group can be processed independently and in parallel. This segmentation allows the system to achieve parallel processing without requiring all rows to be processed simultaneously, thus reducing hardware size while maintaining reduced processing time.
2Loss of time
If parallel updating of all rows is used, then processing time is reduced, but hardware size increases
Solution Approach 1:
Rather than processing all rows in parallel (which would require large hardware), the rows are segmented into groups that can be processed in parallel. This partial parallelization achieves a balance between processing time reduction and hardware size constraints.
3Loss of time
If parallel updating of many rows is used, then processing time is reduced, but synchronization overhead increases
Solution Approach 1:
The rows are divided into groups where rows within each group can be updated in parallel without requiring synchronization with other groups. This segmentation minimizes the frequency and complexity of synchronization operations while still achieving significant parallel processing speedup.
Solution Approach 2:
The parity-check matrix is pre-processed to identify and group rows that can be safely updated in parallel. This preliminary organization eliminates the need for complex runtime synchronization logic, reducing device complexity while maintaining processing speed benefits.
Data Source
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Figure 2a~2b
Figure 3a~3b
AI summary
Disclosed is a method for accelerating bit error correction in a receiver in a radio communication network such as (5)G NR, wherein the receiver is configured to update soft bit values associated with each code bit of a block code based on parallel parity checks. The method comprises receiving (101) a block code encoded message, and for any group of two or more rows of a parity-check matrix of the block code: when the two or more rows are nonoverlapping (102): combining (103) the two or more rows in a row group for parallel updating, updating (104), in parallel, the parity checks of the row group for the received message, and forming (107) a message estimate based on the updated parity checks. Corresponding computer program product, apparatus, and receiver are also disclosed. Some embodiments further comprise, when the two or more rows are overlapping in one shared bit: combining (105) the two or more rows in a row group for parallel updating, updating (106) the parity checks of the row group for the received message by: collecting (106a) available bit-to-check values except from the shared bit, computing (106b) shared check-to-bit values towards the shared bit based on the collected bit-to-check values, computing (106c) shared bit-to-check values for the shared bit based on the computed shared check-to-bit values, computing (106d) new check-to-bit values for all remaining bits, and parallel updating (106e) of the parity checks of the row group for the received message based on the computed check-to-bit values.