LDPC Row Orthogonality for Flexible Decoder Scheduling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing wireless communication systems face challenges in efficiently encoding and decoding data using low-density parity-check (LDPC) codes, particularly in maintaining performance while allowing for flexible scheduling and hardware processing.
Innovation Solution
The implementation of LDPC codes with pairwise orthogonality of adjacent rows in the parity check matrix (PCM) enables flexible encoder/decoder scheduling without performance loss, utilizing new hardware components and encoding/decoding techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codes are used for encoding and decoding in wireless communication systems, then error correction capability is improved, but hardware processing complexity and scheduling flexibility are worsened
Solution Approach 1:
The parity check matrix is divided into multiple blocks, where each block corresponds to a specific set of check nodes. This segmentation allows the decoding process to be divided into independent stages, where each stage processes a specific block of the matrix. The segmented structure enables parallel processing of different blocks, reducing overall hardware complexity while maintaining error correction capability.
Solution Approach 2:
The patent implements dynamic scheduling of decoding operations based on the segmented block structure. Different blocks can be processed in different orders or simultaneously depending on hardware availability and error patterns. This dynamic approach allows flexible resource allocation and scheduling, reducing hardware processing complexity while maintaining reliability.
2Reliability
If traditional LDPC decoding is implemented, then error correction is achieved, but scheduling flexibility and processing speed are reduced
Solution Approach 1:
By segmenting the parity check matrix into multiple blocks that can be processed independently, the decoding process can proceed in parallel across different hardware units. This segmentation enables pipelining and concurrent processing, significantly increasing processing speed while maintaining error correction capability.
Solution Approach 2:
The patent performs preliminary organization of the parity check matrix into a standardized block structure before decoding begins. This preliminary arrangement pre-computes and pre-organizes the decoding operations, allowing faster execution during actual decoding. The base graph structure is prepared in advance, enabling rapid processing during communication operations.
3Measurement precision
If rigid decoding schedules are used, then decoding accuracy is maintained, but hardware utilization and processing efficiency are reduced
Solution Approach 1:
The patent implements dynamic scheduling that adapts to hardware availability and error patterns while maintaining decoding accuracy. The segmented block structure allows the scheduler to dynamically allocate processing resources to different blocks based on current system state, improving hardware utilization without sacrificing decoding performance.
Solution Approach 2:
The patent changes the structural parameters of the LDPC code by using a base graph with specific block structures and connectivity patterns. This parameter optimization allows for more flexible scheduling while maintaining or improving decoding accuracy. The base graph parameters are specifically chosen to enable efficient parallel processing and dynamic scheduling.
Data Source
AI summary
Certain aspects of the present disclosure provide low-density parity-check (LDPC) codes having pairwise orthogonality of adjacent rows, and a new decoder that exploits the pairwise row orthogonality for flexible decoder scheduling without performance loss. An apparatus includes a receiver configured to receive a codeword in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximal the receiver. The apparatus includes at least one processor coupled with a memory and comprising decoder circuitry configured to decode the codeword based on a LDPC code to produce a set of information bits. The LDPC code is stored in the memory and defined by a base matrix having columns in which all adjacent rows are orthogonal in a last portion of the rows.