LDPC Decoder Row-Wise Scanning to Cut Memory and Iterations
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Solution Overview
Problem
Existing LDPC decoding methods face challenges with high storage capacity and complex algorithms, leading to performance losses and inefficient hardware resource utilization.
Innovation Solution
An LDPC decoding method that reduces storage capacity and number of iterations by utilizing a Row-Wise Scanning Round and Column-Wise Scanning Round phase, employing a recovery circuit, search module, and adding circuit in a multi-way parallel operation mode, with simplified LLR operations and reduced memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flood-type update structure is used, then any form of check matrix can be supported, but storage capacity is doubled and update rate is slower
Solution Approach 1:
The patent segments the update process into two distinct phases: RWSR phase for row-wise updates and CWSR phase for column-wise updates. This segmentation allows the system to avoid storing all intermediate variables simultaneously, reducing storage capacity while maintaining support for various check matrix forms through structured phase-based processing.
Solution Approach 2:
The patent implements dynamic switching between different update modes (RWSR and CWSR phases) depending on the processing stage. This dynamic approach allows the system to adapt its storage requirements and update rate characteristics, achieving a balance between storage capacity and processing speed while maintaining versatility for different check matrix types.
2Quantity of substance
If horizontal or vertical structure is used, then memory is halved and convergence rate is doubled, but algorithm implementation is more complicated
Solution Approach 1:
The patent divides the decoding process into RWSR and CWSR phases with distinct update rules for each phase. This segmentation simplifies the implementation within each phase while achieving reduced memory requirements and improved convergence, as each phase handles specific update operations independently with well-defined procedures.
Solution Approach 2:
The patent employs periodic alternation between RWSR phase and CWSR phase in a structured sequence. This periodic action pattern simplifies implementation by establishing a regular, repeating cycle of operations, making the algorithm more manageable while achieving the desired memory reduction and convergence rate improvement.
3Productivity
If parallel processing is used, then decoding speed is maximized, but hardware resources consumption is biggest
Solution Approach 1:
The patent segments parallel processing into two phases (RWSR and CWSR), where each phase processes specific sets of variables in parallel. This segmentation reduces the peak hardware resources required at any given moment compared to fully parallel processing, while still maintaining high decoding speed through phase-based parallelism.
Solution Approach 2:
The patent implements dynamic adjustment of parallelism level by switching between RWSR phase with certain parallel degree and CWSR phase with different parallel degree. This dynamic approach allows the system to optimize the balance between decoding speed and hardware resource consumption based on the current processing stage and system capabilities.
Data Source
AI summary
The invention relates to the field of decoders, more specifically, to a decoding method of LDPC (Low Density Parity Check Code). The decoding method comprising: in the rwsr (Row-Wise Scanning Round) phase, the recovery circuit reads a plurality of sign bits, the absolute value of a minimum value, the absolute value of a second smallest value and the absolute value of a third smallest value which are stored previously, and they are output by a comparison and a selector, the output of the comparator and selector is shifted, and then is combined with each sign bit to obtain an update message of the previous check node, the update message is subtracted from the posterior probability by the addition circuit to obtain an input of the update unit.