LDPC Decoding with Selective LLR Updates for Higher Throughput
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Solution Overview
Problem
Current LDPC code decoders face challenges in achieving high decoding throughput and efficiency, particularly in 5G and beyond communication systems, which require processing billions of bits per second, leading to increased complexity and hardware requirements such as larger chips and higher power consumption.
Innovation Solution
The method involves iterative decoding with reduced operations by determining and estimating log-likelihood ratios (LLRs) only for specific subsets of codeword bits, skipping unnecessary calculations based on syndrome checks, and optimizing hardware implementation to reduce processing time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full iterative decoding is performed for all codeword bits, then error-correction performance is improved, but operation complexity and processing time increase
Solution Approach 1:
The patent segments the codeword bits into two subsets: information bits and parity bits. The decoding process is then segmented to perform full iterative decoding only on information bits while using simplified syndrome-based checking for parity bits. This segmentation allows the system to maintain high error-correction performance for the critical information bits while reducing overall operational complexity by avoiding redundant full decoding operations on parity bits.
Solution Approach 2:
The patent applies partial action by performing complete iterative decoding operations only on the necessary information bits rather than on all codeword bits. For parity bits, only essential syndrome checks are performed. This partial approach maintains sufficient error-correction performance while significantly reducing the number of operations required, thereby lowering computational complexity and processing time.
2Productivity
If high decoding throughput is achieved for 5G systems, then data transmission efficiency is improved, but hardware requirements and power consumption increase
Solution Approach 1:
The patent segments the decoding workload by distinguishing between information bits requiring full iterative decoding and parity bits requiring only syndrome checks. This segmentation enables the hardware to process different bit types through different operational paths, improving overall decoding throughput by optimizing resource allocation while reducing power consumption through selective application of computationally intensive operations only where necessary.
Solution Approach 2:
The patent changes the operational parameters applied to different subsets of codeword bits. Information bits undergo full iterative decoding with multiple LLR calculations and updates, while parity bits use simplified syndrome-based parameters. This parameter differentiation allows the system to achieve high decoding throughput by processing bits at different complexity levels, thereby reducing average power consumption while maintaining high overall productivity.
3Reliability
If LDPC code length is increased to improve error correction, then reliability is improved, but processing time and hardware area increase
Solution Approach 1:
The patent segments long codewords into information bits and parity bits, applying different decoding strategies to each segment. For long codes, this segmentation is particularly beneficial as it allows the system to focus computational resources on decoding information bits while using efficient syndrome checks for parity bits, thereby maintaining high error-correction capability for extended code lengths without proportionally increasing processing time.
Solution Approach 2:
The patent applies partial decoding actions to long codewords by performing complete iterative decoding only on information bits and simplified syndrome-based verification on parity bits. This partial approach enables the system to handle longer code lengths with improved error-correction capability while avoiding the proportional increase in processing time that would result from applying full decoding operations to all bits in the extended codeword.
Data Source
AI summary
The disclosure relates to a method performed by an apparatus for decoding an encoded signal in a communication system according to an embodiment of the disclosure may include an operation of receiving an encoded signal including a plurality of codeword bits, an operation of determining a first log-likelihood ratio (LLR) for the plurality of codeword bits, and an operation of performing iterative decoding a predetermined number of times based the first LLR, and the plurality of codeword bits may include a codeword bit included in a first subset and a codeword bit included in a second subset, and the operation of performing iterative decoding may include determining a second LLR only for the codeword bit included in the first subset of the plurality of codeword bits, and estimating, based on the second LLR, a bit value only for the codeword bit included in the first subset.