LDPC Bit Interleaver Sequencing for 256-Symbol Burst Error Distribution
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation unless burst errors in digital broadcast channels are effectively distributed, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 16200 and a code rate of 2/15, using a processor to generate an interleaved codeword on a bit group basis, with a specific permutation order for 256-symbol mapping, optimized for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bit interleaver is designed for specific LDPC coder parameters and modulation order, then performance is improved, but adaptability deteriorates
Solution Approach 1:
The patent applies parameter changes by providing multiple interleaving sequences specifically designed for different modulation orders (e.g., 64-QAM, 256-QAM) and LDPC coder configurations. The system selects and applies the appropriate interleaving sequence based on the specific modulation order and code rate being used, thereby optimizing performance for each parameter combination while maintaining adaptability through selective application.
Solution Approach 2:
The patent implements dynamics by making the interleaver configuration adaptive rather than fixed. The system dynamically selects among multiple pre-defined interleaving sequences based on the operating conditions (modulation order, code rate), allowing the interleaver to adapt its behavior to match the specific transmission parameters without requiring a completely different design for each scenario.
2Reliability
If burst errors are distributed via bit-by-bit interleaver, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the interleaving process into distinct stages: bit-group-level interleaving and symbol-level interleaving. The bit-by-bit interleaver operates on segmented bit groups rather than the entire codeword at once, and works in conjunction with a symbol interleaver that processes modulated symbols. This segmented approach distributes burst errors effectively while keeping each individual interleaving stage relatively simple.
Solution Approach 2:
The patent implements universality by designing the bit-by-bit interleaver to work with multiple modulation orders and LDPC coder configurations through the use of multiple pre-defined interleaving sequences. A single interleaver structure can serve multiple functions across different transmission scenarios by selecting the appropriate sequence, avoiding the need for completely separate interleavers for each modulation scheme.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.