LDPC Transmitter Shortening Pattern for BER and FER Stability

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Solution Overview

Problem

Current digital broadcasting systems face challenges in providing improved performance, particularly in achieving better bit error rates (BER) and frame error rates (FER) due to limitations in signal transmission and reception methods.

Innovation Solution

A transmitter is designed with an outer encoder, zero padder, and LDPC encoder to encode input bits, pad zero bits, and map them based on a preset shortening pattern to ensure the required number of bits for LDPC encoding, thereby improving BER and FER performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If zero bits are padded to meet the required number of bits for LDPC encoding, then the code length and code rate requirements are satisfied, but the bit error rate (BER) and frame error rate (FER) performance deteriorates

Engineering Contradiction:
Improvecode length and code rate adaptabilityVSAvoidbit error rate and frame error rate performance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-determining optimal shortening patterns before encoding. The transmitter and receiver agree on specific patterns for removing information bits, allowing the system to adapt code length and rate while maintaining BER and FER performance. This is achieved by systematically selecting which bit positions to shorten based on predetermined patterns rather than arbitrary or sequential shortening.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies local quality by making different parts of the code structure serve different functions. Specifically, certain bit positions are designated for shortening while others are preserved for information transmission. The shortening pattern creates local variations in the code structure, with some bit groups having reduced weight or different protection levels, optimizing both adaptability and reliability.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If information bits are sequentially disposed in bit groups for encoding, then the encoding process is simplified, but the bit error rate (BER) and frame error rate (FER) performance is suboptimal

Engineering Contradiction:
Improveencoding process simplicityVSAvoidbit error rate and frame error rate performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-defining non-sequential shortening patterns before the encoding process. These patterns are established in advance and agreed upon by both transmitter and receiver, allowing the system to achieve optimal BER and FER performance without complicating the actual encoding operation. The complexity is moved to the pattern design stage rather than the encoding execution stage.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10382165B2Transmitter and shortening method thereof
Publication Date: 2019.08.13 SAMSUNG ELECTRONICS CO LTD
  • US10382165B2 patent drawing
  • US10382165B2 patent drawing
  • US10382165B2 patent drawing

AI summary

A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, determine whether a number of the outer-encoded bits satisfies a predetermined number of bits required according to at least one of a code rate and a code length for Low Density Parity Check (LDPC) encoding, pads zero bits to some of the bits in the bit groups if the number of the outer-encoded bits is less than the predetermined number of bits, and maps the outer-encoded bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute LDPC information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the some of the bits, in which zero bits are padded, are included in some of the bit groups which are not sequentially disposed in the LDPC information bits.