LDPC Transmitter Shortening Layout for BER and FER Control
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Solution Overview
Problem
Current signal transmitters and receivers face challenges in efficiently managing bit error rates and frame error rates due to limitations in existing broadcasting communication standards, particularly in digital broadcasting services that require various receiving schemes for high-definition digital television and portable broadcasting.
Innovation Solution
A transmitter is designed with an outer encoder, zero padder, and LDPC encoder to encode input bits, generate parity bits, and pad zero bits based on a predetermined shortening pattern, forming Low Density Parity Check (LDPC) information bits, which are then encoded to improve bit error rate (BER) and frame error rate (FER) performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If zero bits are padded to remaining bits in bit groups based on a predetermined shortening pattern, then bit error rate (BER) and frame error rate (FER) performance is improved, but device complexity increases due to additional encoding steps and pattern management
Solution Approach 1:
The patent applies preliminary action by pre-defining shortening patterns that specify which bit groups receive zero-padding. These patterns are determined in advance based on the number of outer-encoded bits, allowing the system to optimize BER and FER performance without real-time complex calculations. The receiver uses the same pre-defined patterns to correctly identify and remove padded zero bits, simplifying the overall system complexity while maintaining high reliability.
2Reliability
If outer-encoded bits are mapped to some bits in bit groups and zero bits are padded to remaining bits, then LDPC information bits are properly constituted, but loss of time occurs due to additional mapping and padding operations
Solution Approach 1:
The patent reduces time loss by pre-calculating and storing shortening patterns that map outer-encoded bits to specific bit group positions. This eliminates the need for complex real-time mapping decisions during encoding. The receiver uses these pre-defined patterns to efficiently identify valid data bits versus padded zero bits, significantly reducing processing time while ensuring proper LDPC information bit constitution.
Solution Approach 2:
The patent segments the LDPC information bits into multiple bit groups, where each group is assigned a specific role (data bits or padded zero bits) based on pre-defined patterns. This segmentation allows parallel processing of different bit groups at the receiver, reducing overall processing time while maintaining the integrity and proper constitution of LDPC information bits.
Data Source
AI summary
A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, maps the outer-encoded bits to some of the bits in the bit groups, and pads zero bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute Low Density Parity Check (LDPC) information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the remaining bits in which zero bits are padded include some of the bit groups which are not sequentially disposed in the LDPC information bits.