LDPC Zero Padding Using Shortening Patterns for Broadcast Signaling
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Solution Overview
Problem
Current channel encoding and modulation techniques for signaling information in broadcast systems lack robustness and efficiency, necessitating the development of new methods optimized for variable length signaling information.
Innovation Solution
A zero padding technique is introduced, where a processor generates an LDPC information bit string by filling specific groups with zeros based on a shortening pattern order, and the remaining groups are filled with a BCH-encoded bit string, optimizing the construction of Bit-Interleaved Coded Modulation (BICM) for efficient transmission and reception of signaling information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional channel encoding and modulation techniques are used for signaling information transmission, then the system can maintain basic functionality, but the robustness and efficiency are insufficient
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the zero-padding length and shortening pattern based on the amount of signaling information. The processor determines the number of zero bits to pad and the shortening pattern order according to the actual information length, transforming fixed parameters into adaptive ones to optimize both robustness and efficiency for different signaling scenarios
Solution Approach 2:
The invention introduces dynamic adaptation in the encoding process by selecting different shortening patterns and zero-padding amounts based on the signaling information length. The system transitions from static encoding parameters to dynamic parameter selection, allowing the encoding scheme to adapt to varying information amounts and channel conditions, thereby improving both reliability and productivity
2Productivity
If zero padding is applied to match LDPC information bit string length with BCH-encoded bit string length, then encoding efficiency is improved, but additional processing complexity is introduced
Solution Approach 1:
The patent applies preliminary action by pre-defining multiple shortening patterns that specify different groups of bit positions for shortening. These patterns are prepared in advance, allowing the processor to quickly select an appropriate pattern based on the information length without performing complex real-time calculations, thus improving encoding efficiency while keeping processing complexity manageable
Solution Approach 2:
The invention segments the LDPC information bit string into groups according to the shortening pattern, where each group corresponds to specific bit positions to be shortened or padded. This segmentation approach simplifies the zero-padding process by organizing bits into manageable groups rather than treating the entire bit string as a single unit, thereby improving encoding efficiency
Data Source
AI summary
A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.