LDPC Block Encoding With SIMD Parallel Shifting and XOR
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Solution Overview
Problem
Conventional software-based LDPC encoders and decoders struggle with scalability, processing speed, and memory utilization efficiency, failing to support all 5G NR standard code cases and exhibiting poor performance in Turbo Decoding Message Passing algorithms.
Innovation Solution
An LDPC encoding and decoding method utilizing data level parallelization and Advanced Vector Extension (AVX)-512 instruction set for SIMD operations, including circular shifting and XOR operations on segmented blocks, to enhance processing speed and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional software-based LDPC encoders and decoders are used, then flexibility and ease of maintenance are improved, but processing speed and scalability deteriorate
Solution Approach 1:
The patent changes the operational parameters of software-based LDPC encoders and decoders by implementing parallel processing architectures and optimizing memory access patterns. This allows the software to achieve hardware-like processing speeds while maintaining the flexibility and ease of maintenance characteristics of software implementations.
2Ease of manufacture
If conventional software-based LDPC encoders and decoders are used, then implementation simplicity is improved, but scalability and support for all 5G NR code cases deteriorate
Solution Approach 1:
The patent segments the LDPC encoding and decoding processes into modular components that can be independently configured and executed. This segmentation enables the software to scale across different code cases specified in the 5G NR standard while maintaining implementation simplicity through a structured, modular architecture.
3Device complexity
If memory utilization efficiency is not optimized, then implementation complexity is reduced, but processing speed deteriorates due to cache miss penalty
Solution Approach 1:
The patent implements preliminary actions by pre-organizing data in memory according to access patterns that minimize cache misses. This includes pre-loading data into buffers and structuring memory layouts to match the parallel processing requirements, thereby improving processing speed without significantly increasing implementation complexity.
Data Source
AI summary
A LDPC encoding method is provided, which is highly scalable and may support a variety of code cases and allow a high processing speed. The LDPC encoding includes: receiving an information sequence to be encoded; segmenting the information sequence into blocks of a predetermined length; deriving parity bits for each of the segmented blocks by using a predetermined parity check matrix; and generating a codeword by combining the parity bits into a corresponding segmented block. The operation of deriving parity bits for each of the segmented blocks includes: performing multiplications with at least one element of the parity check matrix by circularly shifting the segmented block a number of times corresponding to the at least one element of the parity check matrix; and performing XOR operations on a plurality of bits of a circularly-shifted segmented block in parallel.