LDPC Soft Decoding Using Adjacent-Cell LLR Modeling

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Solution Overview

Problem

Existing LDPC soft decoding methods for non-volatile memories, such as flash memory, face challenges in improving error correction capability and reducing bit error rates, particularly due to the influence of adjacent memory cells on the distribution of current memory cells, which affects storage performance.

Innovation Solution

A method for performing LDPC soft decoding that considers the comprehensive distribution of a current memory cell influenced by adjacent cells, using a pre-established LLR table that includes storage time, threshold voltage partition, and comprehensive distribution to determine an LLR value, thereby improving decoding accuracy and reducing bit errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing LDPC soft decoding methods are used for non-volatile memories, then the decoding process can be performed, but the error correction capability is insufficient and bit error rate is high due to ignoring the influence of adjacent memory cells

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent pre-calculates and stores LLR values in a lookup table before actual decoding operations. The comprehensive distribution considering adjacent cell influences is computed in advance, and the resulting LLR values are stored for direct retrieval during decoding, eliminating the need for complex real-time calculations and significantly reducing decoding complexity while maintaining high error correction capability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates a simplified model by copying the essential characteristics of the complex physical phenomenon (adjacent cell influences) into a pre-computed lookup table. Instead of simulating the full complex interactions during decoding, the patent uses pre-calculated LLR values that capture the essential effects, achieving accurate error correction with reduced computational complexity

Inventive Principle:
Principle #26Copying

2Measurement precision

If the influence of adjacent memory cells is considered in the decoding process, then the bit error rate is reduced, but the calculation complexity increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidcalculation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent performs the complex calculation of comprehensive distributions and LLR values in advance, before actual decoding operations. By pre-computing these values and storing them in a lookup table, the patent achieves high decoding accuracy through precise LLR values while avoiding the computational burden during real-time decoding operations

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a lookup table as an intermediary structure that stores pre-computed LLR values. This intermediary allows the system to access precise decoding information without performing complex calculations during the actual decoding process, effectively decoupling the complexity of accurate LLR computation from the decoding operation itself

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12068757B2Method for performing LDPC soft decoding, memory, and electronic device
Publication Date: 2024.08.20 INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
  • US12068757B2 patent drawing
  • US12068757B2 patent drawing
  • US12068757B2 patent drawing

AI summary

The method includes: reading a memory cell having a encoded information bit, so as to obtain an LLR value of a current memory cell with reference to a pre-established LLR table according to a storage time, a threshold voltage partition and a comprehensive distribution corresponding to the current memory cell during reading; and performing a soft decoding operation on a codeword in the memory cell having the encoded information bit according to the read LLR value of the current memory cell, wherein the comprehensive distribution of the current memory cell is determined according to an influence of a memory cell adjacent to the current memory cell on a distribution of the current memory cell; an input of the pre-established LLR table comprises a storage time, a threshold voltage partition and a comprehensive distribution, and an output of the pre-established LLR table comprises an LLR value.