LDPC Bit-Flipping Decoder Stall Detection for Low Error Floor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional bit flipping decoders in memory systems have high error floors, leading to a high probability of failing to decode input data correctly, even when the error rate in input bits is low, due to getting trapped in local maximum/minimum points during iterative decoding operations.
Innovation Solution
Implementing a stall detector to determine when the error recovery progress is stalled and switching between static and dynamic syndrome modes to change the bit selection operation, allowing the decoder to escape local maxima/minima and improve decoding iterations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bit flipping decoding is used, then the decoding process is simple and fast, but the error floor is high leading to frequent miss-corrections
Solution Approach 1:
The patent implements dynamic mode switching between static syndrome mode and dynamic syndrome mode based on real-time detection of stalling conditions. The stall detector monitors decoding progress and triggers mode transitions when stagnation is detected, allowing the decoder to adapt its behavior dynamically to escape local maxima/minima and improve reliability without permanent structural complexity
Solution Approach 2:
The stall detector provides feedback about decoding progress to the mode controller, which then adjusts the bit selection operation accordingly. This feedback mechanism enables the system to detect when conventional bit flipping becomes trapped and switches to dynamic syndrome mode to escape the trap, resolving the contradiction between simple operation and high reliability
2Reliability
If static syndrome mode is used throughout, then the operation is straightforward, but the decoder gets trapped in local maxima/minima causing high error floor
Solution Approach 1:
The system transitions from purely static syndrome mode to a dynamic system that switches between static and dynamic syndrome modes based on stalling detection. This dynamic adaptation maintains ease of operation during normal decoding while improving reliability when trapped in local maxima/minima by activating dynamic syndrome mode
Solution Approach 2:
The patent changes the operational parameter (syndrome calculation method) from static to dynamic based on the detected stalling condition. When the stall detector identifies that progress has stalled, the system changes the bit selection parameter from static syndrome-based selection to dynamic syndrome-based selection, escaping the local maximum/minimum trap
3Reliability
If dynamic syndrome mode is used throughout, then the error floor is reduced, but the computational complexity and power consumption increase
Solution Approach 1:
Instead of continuously applying the more complex dynamic syndrome mode, the system applies it partially and selectively only when stalling is detected. The majority of decoding operations use the simpler static syndrome mode, consuming less power, while dynamic mode is activated temporarily only when needed to escape local maxima/minima, achieving improved reliability without proportional increase in power consumption
Solution Approach 2:
The system dynamically adjusts its operational mode based on real-time conditions, switching from low-power static syndrome mode to higher-power dynamic syndrome mode only when necessary. This dynamic adaptation ensures that power consumption increases only when needed to resolve decoding stalls, rather than maintaining high power consumption continuously
Data Source
AI summary
A memory device having a Low-Density Parity-Check (LDPC) decoder that is energy efficient and has a low error floor. The decoder is configured to determine syndromes of bits in a codeword, select bits in the codeword based at least in part on the syndromes according to a first mode, and flip the selected bits in the codeword. The decoder can repeat the bit selection and flipping operations to iteratively improve the codeword and reduce parity violations. Further, the decoder can detect a pattern in parity violations of the codeword in its iterative bit flipping operations. In response, the decoder can change from the first mode to a second mode in bit selection for flipping. For example, the decoder can transmit from a dynamic syndrome mode to a static syndrome mode in response to the pattern of repeating a cycle of bit flipping iterations.