LDPC Stochastic Decoding with Scaled Probability Messages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current stochastic decoding methods for LDPC codes on factor graphs are complex and costly, and fail to successfully decode state-of-the-art capacity-approaching codes, particularly due to sensitivity to switching activity and the 'latching' problem, which limits their hardware implementation and performance.
Innovation Solution
A method and system for stochastic decoding of LDPC codes using a factor graph representation, where probability messages are scaled or up-scaled to maintain switching activity, and processed through logic circuitry with equality and parity check nodes to determine an estimated sequence of information bits, incorporating techniques like noise-dependent scaling and lookup tables to prevent node locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If stochastic decoding is implemented using simple circuitry, then hardware complexity is reduced, but decoding performance deteriorates due to the latching problem and sensitivity to switching activity
Solution Approach 1:
The patent applies preliminary action by pre-processing the encoded samples through scaling or up-scaling operations before stochastic decoding. This preliminary step adjusts the switching activity levels to prevent latching problems during the actual decoding process, thereby maintaining decoding performance while using simple stochastic circuitry.
Solution Approach 2:
The patent changes the parameter of switching activity level through scaling factors applied to the encoded samples. By adjusting this parameter before decoding, the system prevents nodes from locking into fixed states (latching problem) while maintaining the simplicity of stochastic computation circuits.
2Ease of operation
If probability messages are not scaled, then computational simplicity is maintained, but switching activity becomes too rare causing nodes to lock into one state
Solution Approach 1:
The patent applies parameter changes by introducing scaling factors that modify the probability messages' switching activity levels. This allows the system to maintain computational simplicity through basic stochastic logic while ensuring sufficient switching activity to prevent node locking.
3Reliability
If complex supernodes with random number generators are added to prevent latching, then decoding reliability improves, but hardware complexity increases significantly
Solution Approach 1:
The patent extracts the complex random number generator functionality from the decoding process and replaces it with simpler scaled probability messages. The scaling operation pre-establishes adequate switching activity without requiring complex supernodes, thereby maintaining reliability while reducing hardware complexity.
Solution Approach 2:
The patent uses simple, disposable scaling operations instead of complex, persistent supernode structures. The scaling factors are applied once to the input messages and then the standard stochastic decoding proceeds with simple logic, avoiding the need for complex random number generation hardware.
4Device complexity
If standard stochastic decoding is used, then hardware implementation is simplified, but capacity-approaching codes cannot be successfully decoded
Solution Approach 1:
The patent applies preliminary scaling to the encoded samples before they enter the simple stochastic decoder. This pre-processing step enhances the signal characteristics to enable successful decoding of capacity-approaching codes while maintaining the simplicity of the hardware implementation.
Data Source
AI summary
The present invention relates to a decoding method and system for stochastic decoding of LDPC codes. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital bits. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the LDPC code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information bits. If an equality node is in a hold state a chosen bit is provided from a corresponding edge memory which is updated by storing output bits from the equality node when the same is in a state other than a hold state.