LDPC Bit Interleaving Structure for Broadcast Symbol Mapping
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Solution Overview
Problem
There is a need for improved decoding and receiving performance in digital broadcasting services, particularly in high quality digital televisions and portable multimedia players, due to the increasing demand for efficient methods to support various receiving methods of digital broadcasting services.
Innovation Solution
A transmitting apparatus and method that includes an encoder for generating an LDPC codeword, an interleaver for rearranging bit groups, and a modulator that maps bits from the LDPC codeword onto modulation symbols, utilizing a parity interleaver, group interleaver, and block interleaver to enhance decoding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit groups are rearranged using multiple interleavers (parity interleaver, group interleaver, block interleaver), then decoding performance is improved, but device complexity increases
Solution Approach 1:
The interleaving process is divided into three distinct segments: parity interleaver (rearranging parity bits), group interleaver (rearranging bit groups), and block interleaver (rearranging blocks of bits). Each segment handles a specific aspect of the data structure, allowing complex rearrangement to be achieved through multiple simpler, specialized components rather than one monolithic complex interleaver.
Solution Approach 2:
The interleaving structure implements nested operations where the parity interleaver operates on individual bits within groups, the group interleaver operates on groups of bits, and the block interleaver operates on blocks containing multiple groups. This nested approach allows systematic processing at multiple levels of granularity, improving decoding performance through hierarchical rearrangement.
2Reliability
If LDPC codeword bits are mapped onto modulation symbols with specific bit group arrangements, then receiving performance is improved, but processing time increases
Solution Approach 1:
The parity interleaver performs preliminary rearrangement of parity bits before the main group interleaving and block interleaving operations. By pre-organizing the parity bit positions according to the LDPC code structure, subsequent mapping operations can proceed more efficiently, reducing the overall processing time while maintaining the performance benefits of systematic interleaving.
Data Source
AI summary
A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.