NAND Flash LDPC Decoding With Syndrome-Weight Early Exit

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Solution Overview

Problem

Current error correction systems in NAND flash storage, particularly LDPC codes, face challenges in latency and processing performance due to iterative decoding processes that consume time and resources, often failing to meet latency and processing requirements in latency-sensitive applications.

Innovation Solution

A data processing system with a controller that includes multiple decoders, allowing for fast decoding with shorter latency when certain conditions are met, and a method for predicting page health by monitoring syndrome weight and iteration number to terminate LDPC decoding early, reducing unnecessary iterations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If iterative decoding process is used for LDPC codes, then error correction performance is improved, but decoding latency and processing time increase

Engineering Contradiction:
Improveerror correction performanceVSAvoiddecoding latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements early termination of the iterative decoding process by monitoring the syndrome weight after each iteration. When the syndrome weight becomes zero (indicating successful error correction) or exceeds a threshold (indicating uncorrectable errors), the decoding process is terminated immediately, skipping unnecessary remaining iterations. This reduces decoding latency while maintaining error correction performance by avoiding redundant processing steps.

Inventive Principle:
Principle #21Skipping (Rushing through)

Solution Approach 2:

The patent introduces a feedback mechanism where the syndrome weight is calculated and monitored after each decoding iteration. This feedback information is used to dynamically control the continuation or termination of the decoding process. The controller adjusts the number of iterations based on the syndrome weight feedback, optimizing the balance between error correction performance and decoding speed.

Inventive Principle:
Principle #23Feedback

2Reliability

If maximum number of iterations is performed, then error correction capability is maximized, but processing burden and power consumption increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies partial action by performing only the necessary number of decoding iterations required to achieve error correction, rather than always executing the maximum number of iterations. The iteration count is dynamically adjusted based on syndrome weight monitoring, performing fewer iterations when errors are corrected early and avoiding unnecessary processing steps, thereby improving processing efficiency while maintaining adequate error correction capability.

Inventive Principle:
Principle #16Partial or excessive action

3Speed

If syndrome weight monitoring is implemented for early termination, then decoding speed is improved, but system complexity increases

Engineering Contradiction:
Improvedecoding speedVSAvoidsystem complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements a self-service mechanism where the decoding process automatically monitors its own syndrome weight and makes termination decisions based on predefined thresholds. The syndrome weight calculation and comparison logic are integrated into the decoding process itself, allowing the system to autonomously determine when to terminate without requiring complex external control mechanisms, thus improving decoding speed with minimal additional complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11177835B2Data storage device
Publication Date: 2021.11.16 SK HYNIX INC
  • US11177835B2 patent drawing
  • US11177835B2 patent drawing
  • US11177835B2 patent drawing

AI summary

A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.