Non-Binary LDPC Decoding with Targeted Symbol Flipping
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Solution Overview
Problem
LDPC decoders often fail to converge or properly decode data, particularly when encountering imperfect codewords or trapping sets in Tanner graphs, leading to decoding failures.
Innovation Solution
A non-binary LDPC decoder with targeted symbol flipping, which involves a controller that changes the values of selected symbols in the Galois Field to facilitate convergence by performing multiple modes of symbol flipping, including flipping one symbol at a time, double symbol flipping across unsatisfied check pools, and generating new unsatisfied check pools, to satisfy parity check constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If normal LDPC decoding is performed using iterative belief propagation, then decoding complexity is kept manageable, but decoding convergence fails when encountering imperfect codewords or trapping sets
Solution Approach 1:
The patent applies preliminary action by performing targeted symbol flipping before resuming normal decoding iterations. When trapping sets or imperfect codewords cause convergence failure, the controller identifies unsatisfied check nodes and flips specific symbol values to transform the problematic codeword into a valid one, enabling subsequent decoding iterations to converge successfully.
Solution Approach 2:
The patent applies parameter changes by modifying symbol values in the Galois Field when decoding stagnation is detected. The controller changes specific symbol parameters (values) based on unsatisfied check node patterns, transforming the input codeword to escape from trapping sets and restore decoding convergence.
2Reliability
If exhaustive symbol flipping is performed to correct all possible errors, then decoding reliability improves, but processing time increases significantly
Solution Approach 1:
The patent applies local quality by performing symbol flipping only in specific locations where errors are most likely to occur. Instead of exhaustive flipping across all symbols, the controller targets symbols connected to unsatisfied check nodes, particularly focusing on the first and second unsatisfied check nodes, thereby reducing processing time while maintaining high error correction capability.
Solution Approach 2:
The patent applies partial action by performing a limited number of targeted symbol flipping operations rather than exhaustive searching. The controller flips symbols selectively based on check node satisfaction status, performing just enough corrections to enable convergence without the overhead of complete exhaustive decoding.
3Measurement precision
If multiple decoding iterations are performed to ensure convergence, then decoding accuracy improves, but computational complexity increases
Solution Approach 1:
The patent applies preliminary action by performing targeted symbol flipping before resuming normal decoding iterations. When trapping sets or imperfect codewords cause convergence failure, the controller identifies unsatisfied check nodes and flips specific symbol values to transform the problematic codeword into a valid one, enabling subsequent decoding iterations to converge successfully.
Solution Approach 2:
The patent applies self-service by enabling the decoding system to automatically detect and correct its own convergence failures. The controller monitors check node satisfaction during iterations and autonomously performs symbol flipping when stagnation is detected, allowing the system to self-correct without external intervention and maintain high decoding accuracy.
Data Source
AI summary
A non-binary low density parity check data decoder comprises a variable node processor operable to update variable node symbol values according to a plurality of elements in a non-binary Galois Field, a check node processor connected to the variable node processor and operable to perform parity check calculations, and a controller operable to perform symbol flipping and to control decoding iterations in the variable node processor and the check node processor.