LDPC Decoding Threshold Updates for NAND Flash Reliability
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Solution Overview
Problem
NAND flash-based storage devices face challenges with higher costs and reduced data reliability due to shorter lifespan and lower noise thresholds, necessitating a more powerful error correction code to improve data integrity.
Innovation Solution
A semiconductor memory system and operating method that employs a bit-flipping LDPC decoding process, where variable nodes are grouped based on column weights to update flipping thresholds and indicators, optimizing error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional BCH codes are used for error correction, then device complexity is lower, but data reliability deteriorates due to shorter lifespan and lower noise thresholds
Solution Approach 1:
The patent applies parameter changes by transitioning from traditional BCH codes to LDPC codes with optimized code rates and structure parameters. The LDPC code uses a parity check matrix with specific density and structure parameters that provide superior error correction performance for NAND flash memory, directly addressing the reliability improvement while managing complexity through parameter optimization
2Reliability
If more powerful error correction code (LDPC) is used to improve data integrity, then data reliability is improved, but decoding complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the LDPC decoding process into multiple iterative steps including syndrome calculation, flipping indicator determination, and threshold updating. The variable nodes are processed in groups through multiple decoding iterations, breaking down the complex decoding task into manageable segments that reduce overall decoding complexity while maintaining high data integrity
Solution Approach 2:
The patent implements dynamics through adaptive threshold updating mechanisms where the flipping threshold is dynamically adjusted based on syndrome values and decoding progress. The decoding process adapts its parameters iteratively, changing thresholds and indicators based on real-time decoding state, which optimizes performance while managing complexity
3Productivity
If conventional decoding methods are used, then device complexity is lower, but decoding speed and accuracy deteriorate
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing flipping thresholds and indicators before the actual decoding process. The system prepares decoding parameters in advance, including pre-computed syndrome values and initial threshold settings, which accelerates the actual decoding operation and improves overall decoding speed while managing complexity through pre-processing
Data Source
AI summary
A semiconductor memory system and an operating method thereof include a plurality of memory devices; and a controller coupled with the memory devices and configured to perform a decoding process to collect at least an output vector associated with an input bit vector, wherein the input bit vector corresponds to a plurality of variable nodes; divide the plurality of variable nodes into a plurality of groups; calculate syndrome of the output vector; and update flipping threshold and flipping indicator of each of the plurality of variable nodes.