LDPC Check Node Transform Approximation Without Lookup Tables
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Solution Overview
Problem
Existing decoding processes, such as LDPC and turbo decoding, face complexity in computing exp and log functions, which are essential for iterative decoding operations, often requiring costly lookup tables and multi-cycle computations.
Innovation Solution
A method that approximates log and exp functions using a simple bit mapping between fixed point fractional and floating point formats, reducing computations to a sequence of additions and subtractions, and leveraging modern floating point arithmetic to avoid complex operations and costly lookup tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If lookup tables are used to directly map transform function F, then decoding accuracy is improved, but hardware resources and device complexity increase significantly
Solution Approach 1:
The patent transforms the complex transform function F(x) into a simplified approximation F^(x) = k - log2(x) by changing the functional form parameters. This approximation maintains decoding accuracy within acceptable bounds while dramatically reducing hardware complexity by eliminating the need for large lookup tables and complex computation circuits.
Solution Approach 2:
The patent replaces expensive, complex lookup tables with a simple mathematical approximation formula that can be computed using basic arithmetic operations. This 'cheap' computational approach achieves sufficient accuracy without requiring the 'expensive' hardware resources of full-precision lookup tables.
2Measurement precision
If exact transform function computation is performed in software, then decoding accuracy is maintained, but processing time and productivity decrease due to multiple computation cycles
Solution Approach 1:
The patent changes the computational parameters by approximating the transform function F(x) with F^(x) = k - log2(x), which can be computed using simple logarithmic operations. This approximation reduces the number of computation cycles required while maintaining sufficient decoding accuracy for practical applications.
Solution Approach 2:
The patent separates the transform function computation into simpler operational steps that can be executed more efficiently. By breaking down the complex transformation into manageable approximation steps, the processing time is reduced while maintaining acceptable accuracy levels.
3Measurement precision
If complex exp and log function computations are performed, then decoding precision is improved, but device complexity and energy consumption increase
Solution Approach 1:
The patent changes the computational approach by using the approximation F^(x) = k - log2(x) instead of computing the full complex exp and log functions. This parameter change maintains sufficient decoding precision while dramatically reducing computation complexity and energy consumption by eliminating the need for complex special function computations.
4Measurement precision
If full precision transform computation is used, then decoding performance is optimized, but processing time increases due to multi-cycle computations
Solution Approach 1:
The patent optimizes the time-performance tradeoff by approximating the transform function with F^(x) = k - log2(x). This approximation maintains sufficient decoding performance while reducing processing time by eliminating multi-cycle computation requirements, as the logarithmic operation can be computed more efficiently than full-precision exp and log functions.
Data Source
AI summary
In modern iterative coding systems such as LDPC decoder and turbo-convolutional decoder in which the invention may be used, the core computations can often be reduced to a sequence of additions and subtractions alternating between logarithm and linear domains A computationally efficient and robust approximation method for log and exp functions is described which involves using a simple bit mapping between fixed point fractional data format and floating point format. The method avoids costly lookup tables and complex computations and further reduces the core processing to a sequence of additions and subtractions using alternating fixed point and floating point processing units. The method is well suited for use in highly optimized hardware implementations which can take advantage of modern advances in standard floating point arithmetic circuit design as well as for software implementation on a wide class of processors equipped with FPU where the invention avoids the need for a typical multi-cycle series of log/exp instructions and especially on a SIMD FPU-equipped processors where log/exp functions are typically scalar.