LDPC Error Correction Circuit for Trapping Set Recovery
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Solution Overview
Problem
Low-density parity check (LDPC) codes face limitations due to trapping sets during iterative decoding, which hinder error correction convergence and resource wastage, even with numerous iterations.
Innovation Solution
An error correction circuit and method that detects trapping sets during iterative decoding, corrects or modifies parameters, and restarts the decoding process from the first iteration or further corrects values of variable nodes to prevent convergence on invalid codewords.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative decoding is performed with numerous iterations to improve error correction capability, then error correction performance is improved, but resource wastage increases due to trapping sets preventing convergence
Solution Approach 1:
The patent applies preliminary action by detecting trapping sets before the iterative decoding process fully completes. The trapping set detector identifies problematic patterns in early iterations, allowing the system to intervene and restart decoding with modified parameters before excessive resources are consumed, thus preventing energy wastage while maintaining error correction capability
Solution Approach 2:
The patent implements feedback through the trapping set detector that monitors the iterative decoding process in real-time. When a trapping set is detected, the system feeds back this information to modify the decoding parameters and restart the process, creating a closed-loop control mechanism that prevents resource wastage while ensuring error correction performance
2Reliability
If trapping set detection and parameter modification are implemented to prevent convergence on invalid codewords, then decoding reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the error correction function into distinct modules: the node processor for iterative decoding, the trapping set detector for monitoring, and the post processor for parameter modification. This modular segmentation allows each component to perform its specific function efficiently, improving decoding reliability while managing circuit complexity through functional decomposition
Solution Approach 2:
The patent introduces an intermediary component - the trapping set detector - that acts as a mediator between the iterative decoding process and the final output. This intermediary monitors the decoding process, identifies trapping sets, and triggers parameter modifications when needed, thereby improving decoding reliability without requiring complete redesign of the entire decoding system
Data Source
AI summary
Disclosed are devices, systems and methods for error correction decoding using an iterative decoding scheme. An error correction circuit includes a node processor to perform a plurality of iterations for updating values of one or more variable nodes and one or more check nodes using initial values assigned to the one or more variable nodes, respectively, a trapping set detector to detect a trapping set in at least one of the plurality of iterations by applying a predetermined trapping set determination policy, and a post processor to reduce at least one of the initial values or invert at least one of values of the variable nodes corresponding to an iteration in which the trapping set is detected, upon detection of the trapping set.