Non-Binary LDPC Decoding with Trellis Maximization
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Solution Overview
Problem
Non-volatile memory arrays, particularly those with multi-level cell (MLC) NAND media, face limited endurance and data corruption issues, making efficient data decoding time-consuming and resource-intensive.
Innovation Solution
The implementation of non-binary LDPC decoders using Trellis Maximization, which efficiently decodes data by generating and utilizing trellises, reducing memory consumption and operating speed, and effectively handling high signal-to-noise ratios with limited precision data representation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-binary LDPC decoding is performed using traditional methods, then decoding accuracy can be maintained, but decoding time and computational resources increase significantly
Solution Approach 1:
The patent segments the set of variable nodes into two distinct subsets: a first subset processed using sum-product algorithm and a second subset processed using min-sum algorithm. This segmentation allows the system to balance between decoding accuracy and computational efficiency by applying different algorithms to different node groups, thereby reducing overall decoding time while maintaining acceptable accuracy levels.
Solution Approach 2:
The patent applies partial action by using the computationally lighter min-sum algorithm for a portion of the variable nodes (the second subset) rather than applying the more accurate but heavier sum-product algorithm to all nodes. This partial application of the simpler algorithm reduces computational burden and decoding time while the sum-product algorithm is still applied to the first subset to maintain decoding accuracy where needed.
2Reliability
If non-binary LDPC decoding is performed using traditional methods, then decoding accuracy can be maintained, but memory consumption increases
Solution Approach 1:
The patent segments the variable nodes into two subsets and applies different algorithms to each, which inherently reduces memory requirements compared to applying the memory-intensive sum-product algorithm to all nodes. The min-sum algorithm used for the second subset requires less memory storage for intermediate calculations, thereby reducing overall memory consumption while maintaining decoding functionality.
3Quantity of substance
If MLC NAND media is used to increase storage capacity, then storage density improves, but endurance and data integrity deteriorate
Solution Approach 1:
The patent segments the decoding process into two algorithmic approaches applied to different variable node subsets. This segmentation enables the system to handle the higher error rates characteristic of MLC NAND media more effectively by using the robust min-sum algorithm for certain nodes while maintaining accuracy through sum-product algorithm for others, thereby improving data integrity preservation in high-capacity MLC storage.
Solution Approach 2:
The patent changes the algorithmic parameters by selecting different decoding algorithms (sum-product vs. min-sum) for different subsets of variable nodes. This parameter change allows the system to adapt to the specific characteristics of MLC NAND media, which has higher error rates, by using the more tolerant min-sum algorithm for certain nodes while maintaining overall decoding accuracy through the combination of approaches.
Data Source
AI summary
Data storage systems may include a solid-state memory array configured to store encoded data units and a controller configured to decode the encoded data units. Decoding the encoded data units may include updating a check node of a plurality of check nodes associated with a parity check matrix by identifying first and second sets of variable nodes in a plurality of variable nodes associated in the parity check matrix with the check node and constructing a trellis based on the second set of variable nodes. The trellis may be used to determine a message and, based at least in part on the message, a first set of messages to be sent from the check node to the first set of variable nodes may be determined. A second set of messages to be sent from the check node to each variable node in the second set of variable nodes also may be determined.