LDPC Decoding with United Node Processing for Faster Convergence
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Solution Overview
Problem
The existing LDPC decoding algorithms face high hardware complexity and memory access delays due to sequential performance of check node and variable node processing, leading to inefficient decoding performance.
Innovation Solution
A decoding algorithm and apparatus that alternately perform check node processing and variable node processing using a united node processor, minimizing memory segmentation and optimizing LLR value updates, allowing simultaneous processing and reducing hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequential check node and variable node processing is used, then hardware complexity is reduced, but decoding convergence speed and throughput deteriorate
Solution Approach 1:
The patent combines check node processing and variable node processing into a single unified processing structure. The unified node processor integrates both processing functions, allowing them to be performed in an alternating manner within the same hardware unit, thereby reducing hardware complexity while improving decoding convergence speed and throughput.
Solution Approach 2:
The patent implements periodic alternating processing between check nodes and variable nodes. The unified node processor switches between processing check nodes and variable nodes in a periodic fashion, which enables efficient utilization of hardware resources while maintaining fast decoding convergence.
2Ease of operation
If separate processing of check nodes and variable nodes is used, then processing clarity is improved, but memory access delays increase
Solution Approach 1:
The patent merges the processing of check nodes and variable nodes into a unified structure that reduces memory access delays. By integrating both processing functions in one unit with shared memory resources, the system eliminates redundant memory access operations that would occur with completely separate processing units.
Solution Approach 2:
The unified node processor performs preliminary preparation of data in memory, organizing it in advance for both check node and variable node processing. This preliminary organization of data reduces the time required for memory access during the alternating processing operations.
3Stability of the object's composition
If more memory segmentation is used, then data organization is improved, but hardware complexity and access delays worsen
Solution Approach 1:
The patent segments memory into distinct regions for storing check node data and variable node data, improving data organization and access efficiency. The memory is divided into check node memory and variable node memory portions, allowing structured storage while being managed by a single unified processor.
Solution Approach 2:
The unified node processor serves multiple functions by handling both check node processing and variable node processing within a single hardware unit. This multi-functional approach reduces hardware complexity compared to having separate dedicated processors for each function.
Data Source
AI summary
A method and apparatus are provided for decoding an LDPC code including a plurality of check nodes and a plurality of variable nodes. The apparatus includes a check node selection scheduler that selects at least one of the check nodes, an LLR memory that stores an input LLR value for the variable nodes as an initial LLR value and stores updated LLR values for variable nodes connected to the selected check node, and a check node message memory that stores a check node message indicating a result value of check node processing on the selected check node. The apparatus further includes at least one united node processor that generates a variable node message by subtracting the check node message of the selected check node from corresponding LLR values read from the LLR memory, performs check node processing on the variable node message, calculates an LLR value updated by adding the variable node message to the check node processing result value, and delivers the calculated LLR value to the LLR memory.