LDPC Decoder Parallel Update Control for Irregular Variable Nodes
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Solution Overview
Problem
Existing LDPC decoders face inefficiencies in utilizing computational resources due to varying degrees of variable nodes, leading to suboptimal throughput and decoding latency when correcting errors in data stored in nonvolatile memory devices.
Innovation Solution
The LDPC decoder employs a mode controller to manage unit logic circuits, updating high-degree variable nodes in single mode and low-degree nodes in multi-mode, allowing for parallel processing of multiple low-degree nodes in one cycle, thereby optimizing resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the LDPC decoder sequentially updates variable nodes with varying degrees, then it can handle irregular LDPC codes, but computational resources are not fully utilized leading to lower throughput
Solution Approach 1:
The patent applies dynamics by making the update mode flexible and adaptable. The mode controller dynamically switches between single-mode and multi-mode operation based on the degree of variable nodes. This allows the system to adapt its computational resource allocation to match the specific requirements of each variable node, thereby fully utilizing available computational resources while maintaining the ability to handle irregular LDPC codes with varying node degrees.
Solution Approach 2:
The patent changes the operational parameter (update mode) based on the degree of variable nodes. When the degree exceeds a threshold, single-mode is used; otherwise, multi-mode is employed. This parameter change strategy optimizes resource utilization by matching the computational complexity to the actual needs of each variable node group,从而提高 throughput without sacrificing adaptability to irregular LDPC code structures.
2Device complexity
If the LDPC decoder uses single-mode for all variable nodes, then resource allocation is simplified, but low-degree variable nodes are processed inefficiently reducing overall throughput
Solution Approach 1:
The patent applies local quality by differentiating the update mode based on the local characteristic (degree) of each variable node. Instead of applying a uniform update mode to all variable nodes, the mode controller selectively applies single-mode to high-degree variable nodes and multi-mode to low-degree variable nodes. This localized optimization ensures that each variable node is processed with the appropriate level of computational resources, thereby maximizing throughput without excessive complexity.
3Productivity
If parallel processing is used for all variable nodes, then throughput is improved, but computational resources are wasted on low-degree variable nodes that require less computation
Solution Approach 1:
The patent applies partial action by selectively applying parallel processing (multi-mode) only to variable nodes that benefit from it (low-degree nodes), while using sequential processing (single-mode) for high-degree nodes where parallel processing would be excessive. This partial application of parallel processing optimizes the balance between throughput improvement and resource utilization, avoiding waste on nodes that don't require intensive parallel computation.
4Measurement precision
If sequential updating is used for high-degree variable nodes, then computational accuracy is maintained, but decoding latency increases
Solution Approach 1:
The patent uses dynamics to switch between single-mode (for accuracy with high-degree nodes) and multi-mode (for speed with low-degree nodes) based on the degree of variable nodes. This dynamic adaptation allows the system to maintain computational accuracy where needed while reducing latency through parallel processing where appropriate, thereby optimizing the trade-off between accuracy and speed.
Data Source
AI summary
A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.