LDPC Variable Node Unit Architecture With Fewer Adder Stages
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Solution Overview
Problem
Existing LDPC decoders face inefficiencies in generating variable node messages due to the need for multiple adder stages and complex operations, which limits their throughput.
Innovation Solution
The proposed solution involves a method and architecture for LDPC decoders where variable node units (VNUs) generate variable node messages by summing specific subsets of check node messages, excluding one message from each subset, and using fewer adder stages to improve processing speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional LDPC decoder architecture is used with multiple adder stages to generate variable node messages, then message generation accuracy is maintained, but throughput is limited due to increased processing time
Solution Approach 1:
The patent segments the variable node message generation process into parallel operations. Instead of using sequential adder stages, the invention divides the check node messages into groups that can be summed simultaneously using parallel adders, thereby reducing the critical path delay and increasing throughput without sacrificing accuracy
Solution Approach 2:
The patent transitions from a sequential time-based processing approach to a parallel spatial-based approach by introducing multiple adder units operating simultaneously. This dimensional change from single-threaded sequential addition to multi-threaded parallel addition resolves the contradiction between maintaining accuracy and improving throughput
2Speed
If fewer adder stages are used to increase throughput, then processing speed improves, but the complexity of message generation logic increases
Solution Approach 1:
The patent merges multiple check node messages into summed values using parallel adder stages, combining multiple input signals simultaneously. This merging approach reduces the number of sequential operations needed while maintaining the necessary computational complexity through spatial parallelism rather than temporal sequencing
3Reliability
If traditional variable node message generation is used, then decoding accuracy is maintained, but the number of adder stages increases circuit complexity
Solution Approach 1:
The patent replaces the traditional sequential mechanical addition process with a parallel addition system. By substituting the sequential adder chain with parallel adder structures, the invention maintains the mathematical accuracy of message generation while reducing the physical circuit complexity and critical path length
Data Source
AI summary
In one embodiment, the present invention is a variable node unit (VNU) of a low-density parity-check (LDPC) decoder. The VNU receives a soft-input value and wc check node messages, where wc is the column hamming weight of the LDPC code. The VNU generates (i) an extrinsic log-likelihood ratio (LLR) by adding all wc check node messages together; (ii) a hard-decision output by adding the extrinsic LLR to the soft-input value and selecting the sign bit of the resulting sum; and (iii) wc variable node messages. Each variable node message is generated by adding a different set of (wc−1) check node messages to the soft-input value where each set excludes a different check node message. In so doing, VNUs of the present invention may generate variable node messages using fewer adder stages compared to prior-art VNUs such that throughput may be increased over that of prior-art VNUs.