LDPC Soft-Decode Verification Using Vth-Based Error Injection
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Solution Overview
Problem
Non-volatile memory devices, such as flash memory, experience increased noise and higher raw bit error rates (RBER) due to decreasing device size, which are exacerbated by program and erase cycles and variability between pages, making it challenging to accurately verify the error correction capabilities of low-density parity-check (LDPC) soft decode systems.
Innovation Solution
A method and system for injecting errors into encoded data based on threshold voltage (Vth) distributions between neighboring logic states, using real data information from memory devices under varying test environments, to verify the soft decode capability of LDPC units by simulating soft read operations and correcting errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device size is decreased to increase storage density, then storage capacity is improved, but noise increases and raw bit error rate increases
Solution Approach 1:
The patent segments the error correction process into two distinct modes: hard-decision decoding for initial error correction and soft-decision decoding for residual error correction. This segmentation allows the system to handle different error types appropriately, improving overall reliability while maintaining high storage density. The hard-decision mode handles common errors efficiently, while the soft-decision mode addresses the increased error rates from smaller device sizes.
Solution Approach 2:
The patent changes the decoding parameters dynamically by switching between hard-decision and soft-decision modes based on error conditions. Soft-decision decoding uses probabilistic information (likelihood ratios) rather than binary decisions, providing more nuanced error correction capability. This parameter change enables the system to maintain low error rates even as device size decreases and storage density increases.
2Duration of action of stationary object
If program and erase cycles are increased to improve data retention, then data storage capability is improved, but noise increases and error rate increases
Solution Approach 1:
The patent applies preliminary error correction using hard-decision decoding before attempting soft-decision decoding. This preliminary action removes the majority of errors introduced by program and erase cycles, reducing the burden on the softer, more resource-intensive soft-decision decoder. By preprocessing the data this way, the system can maintain data retention across many P/E cycles while managing error rates effectively.
Solution Approach 2:
The patent introduces an intermediary hard-decision decoding stage that acts as a mediator between the noisy memory output and the soft-decision decoder. This intermediary layer cleans up obvious errors before they reach the soft-decision process, improving the overall reliability of the system even after multiple program and erase cycles have degraded the data.
3Reliability
If soft decode capability is enhanced to correct more errors, then error correction capability is improved, but decoding complexity increases
Solution Approach 1:
The patent applies partial soft-decision decoding only when necessary, after hard-decision decoding has been performed. Rather than applying full soft-decision decoding to all data (which would maximize complexity), the system uses partial action - only engaging the complex soft-decision process for errors that survive the initial hard-decision pass. This reduces overall decoding complexity while maintaining strong error correction capability for the most difficult errors.
Solution Approach 2:
The patent implements a dynamic decoding architecture that adapts between hard-decision and soft-decision modes based on the error characteristics of the incoming data. The system dynamically selects the appropriate decoding complexity level, using simple hard-decision decoding when errors are few and straightforward, and escalating to more complex soft-decision decoding only when necessary. This dynamic approach balances error correction capability with decoding complexity.
4Measurement precision
If threshold voltage distributions are modeled accurately to improve error injection, then verification accuracy is improved, but processing time increases
Solution Approach 1:
The patent performs preliminary error injection using simplified threshold voltage distribution models during the verification process. By injecting errors based on pre-characterized distribution patterns rather than performing complex real-time simulations, the system achieves high verification accuracy without excessive processing time. The preliminary modeling of threshold voltage distributions allows for efficient error pattern generation that accurately reflects real memory behavior.
Data Source
AI summary
A method for verifying a low-density parity-check (LDPC) unit capable of being applied in a memory system can include receiving original data corresponding to a memory device, encoding the original data by the LDPC unit to be verified, injecting errors into the encoded original data by a data pattern for generating verifying data, and verifying a soft decode capability of the LDPC unit by utilizing the verifying data. The data pattern can include the errors generated by threshold voltage (Vth) distributions interlaced between two neighboring logic states of 2n logic states of the memory device. The method and system can provide an error injection to accurately and efficiently verify a LDPC soft decode capability of the LDPC unit, decrease errors, increase error correction accuracy and efficiency, more accurately model actual threshold voltage (Vth) distributions, increase flexibility, increase speed, increase performance, and reduce firmware overhead.