LDPC Decoding with Pre-Characterized Weak Bits in Memory Cells
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Solution Overview
Problem
As more bits are stored per memory cell in storage devices, the reliability and endurance of non-volatile memory devices are reduced due to increased device and circuit noise, leading to higher error rates, which are exacerbated by the need for more complex LDPC error correction that slows down the overall performance.
Innovation Solution
Pre-characterizing weak cell information by identifying fast and slow cells in the memory device and converting this information into Log-Likelihood Ratio (LLR) values to be used by the LDPC engine for faster decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more bits are stored per memory cell to increase storage capacity, then storage density is improved, but error rates increase due to increased device and circuit noise
Solution Approach 1:
The patent applies preliminary action by pre-characterizing weak bits before the actual read operation. During a separate characterization phase, the system identifies bits that are prone to errors due to threshold voltage window issues. This pre-identification allows the LDPC decoder to allocate additional correction resources to these specific bits during the read operation, rather than treating all bits uniformly. This resolves the contradiction by preparing correction strategies in advance, enabling high-density storage while maintaining reliability through targeted error correction.
2Reliability
If LDPC correction capability is improved by providing weak bit information to the LDPC engine, then error correction reliability is improved, but processing time increases
Solution Approach 1:
The patent resolves this contradiction by performing the time-consuming weak bit identification and characterization in advance, during a separate pre-characterization phase. The results of this preliminary analysis are stored and reused during subsequent read operations. This allows the LDPC engine to quickly access pre-identified weak bit locations without performing the full characterization analysis during the actual read, thus maintaining high error correction capability while minimizing processing time overhead.
Solution Approach 2:
The patent applies periodic action by performing weak bit characterization periodically or intermittently rather than continuously for every read operation. The system can update weak bit information based on wear cycles, temperature changes, or other conditions that affect threshold voltage. This periodic updating strategy maintains accurate weak bit information for reliable error correction while avoiding the time penalty of continuous re-characterization, thus balancing reliability and processing speed.
3Measurement precision
If the LDPC engine determines weak cells in real-time to improve correction accuracy, then error correction precision is improved, but decoding speed decreases
Solution Approach 1:
The patent resolves this contradiction by performing weak cell determination in advance during a pre-characterization phase, separate from the actual read and decode operations. The system identifies weak cells based on threshold voltage analysis and stores this information for later use. During the actual read operation, the LDPC engine simply retrieves the pre-determined weak cell locations and applies appropriate correction weights, eliminating the need for time-consuming real-time analysis while maintaining high correction accuracy.
Data Source
AI summary
A storage device may speed up error correction by pre-characterizing weak cell information in a memory device. The storage device includes a memory device with cells that may store multiple bits. A controller executes a pre-characterization operation on the memory device to identify a slow cell and/or a fast cell on the memory device. The controller retrieves weak cell information for the slow cell and/or the fast cell. The controller converts the weak cell information into values used by an error correction engine and provides the values to the error correction engine to be used in decoding information retrieved from the memory device.