LDPC Sub-Block XOR Coding to Eliminate Error Floors
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Solution Overview
Problem
Low Density Parity Check (LDPC) codes exhibit an error floor at high Signal-To-Noise Ratios due to structures like trapping sets and absorbing sets, making it difficult to guarantee performance in communication and storage systems, especially in Hard Disk Drives where stringent error recovery is required.
Innovation Solution
The proposed method uses an additional layer of error correction by dividing user data into sub-blocks, encoding each with a first LDPC code, computing a bitwise XOR, and then encoding the result with a second LDPC code, which eliminates the error floor without requiring additional hardware, using a small fraction of parity overhead and allowing flexibility in implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If LDPC codes are used to achieve performance close to theoretical maximum, then communication efficiency is improved, but error floor performance deteriorates due to trapping sets and absorbing sets
Solution Approach 1:
The patent segments the LDPC code into multiple sub-blocks and processes them through multiple decoding passes. The first decoding pass handles the majority of error correction, while subsequent passes address remaining errors in segmented portions, effectively breaking down the error floor problem caused by trapping sets.
Solution Approach 2:
The patent performs preliminary error correction in the first decoding pass before addressing the error floor issue. By pre-correcting the majority of errors and preparing the data structure, subsequent decoding passes can more effectively target and eliminate the remaining errors that cause the error floor.
2Reliability
If code construction is optimized to reduce error floor, then error correction performance is improved, but device complexity increases due to exponential increase in optimization difficulty for code lengths above 3000-4000 bits
Solution Approach 1:
The patent divides the complex code construction optimization problem into manageable segments by processing the code in multiple passes with different decoding strategies. Each pass handles specific aspects of error correction, making the overall complex problem tractable through systematic segmentation of the decoding process.
Solution Approach 2:
The patent employs dynamic decoding strategies that adapt based on the decoding state. The system transitions between different decoding approaches in different passes, adjusting the complexity of processing based on the remaining error patterns, thereby managing device complexity while maintaining high error correction performance.
3Reliability
If code length is increased to improve error floor performance, then error correction capability is improved, but hardware implementation complexity increases due to large memory requirements
Solution Approach 1:
The patent segments the long code into multiple sub-blocks that can be processed independently in different decoding passes. This segmentation allows the hardware to handle long codes by processing smaller portions sequentially, reducing the peak memory requirements while maintaining the benefits of long code error floor performance.
Solution Approach 2:
The patent introduces a temporal dimension to the decoding process by using multiple passes. Instead of requiring all resources simultaneously, the system distributes the processing across time, allowing the same hardware resources to be reused in different passes, thereby reducing overall hardware complexity while handling long codes.
4Reliability
If additional error correction scheme is added to correct remaining errors, then error correction performance is improved, but parity overhead increases because it is the multiple of user data length
Solution Approach 1:
The patent makes the existing LDPC code structure multi-functional by using it in multiple decoding passes with different strategies. The same code structure serves both the initial error correction and the subsequent error floor mitigation, eliminating the need for separate additional error correction codes and their associated overhead.
Solution Approach 2:
The LDPC code structure is designed to serve multiple purposes through iterative decoding. The same parity bits and code structure that provide initial error correction capability are reused in subsequent passes to address error floor issues, making the system self-sufficient and avoiding additional overhead from separate correction schemes.
5Reliability
If additional error correction hardware is added to eliminate error floor, then error correction performance is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent makes the existing LDPC decoding hardware multi-functional by configuring it to perform multiple decoding passes with different strategies. The same hardware resources are reused across passes, eliminating the need for additional dedicated error correction hardware while achieving improved error floor performance.
Solution Approach 2:
The patent implements periodic decoding passes that cycle through different decoding strategies. The hardware alternates between different decoding modes in successive passes, using the same physical resources periodically for different functions, thereby avoiding the need for additional hardware while maintaining continuous error correction capability.
Data Source
AI summary
The proposed method presents a novel error correction scheme utilizing LDPC codes that provides desired error floor performance. The error floor performance is achieved through combination of the two design parameters of the method. Encoding a block of user data of length S*K bits includes (A) dividing the block into S sub-blocks of equal length, each sub-block having K bits; (B) encoding each of the sub-blocks using a first Error-Correcting-Code; (C) computing bit-wise XOR of all the sub-blocks, thereby generating a new sub-block of K bits; and (D) encoding the new sub-block using a second Error-Correcting-Code.