LDPCCC Decoder Architecture With Fixed RAM Mapping for High Throughput
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Solution Overview
Problem
Existing decoder architectures for low-density parity-check convolutional codes (LDPCCCs) face limitations in achieving high throughput and low hardware complexity, particularly for time-varying codes, and are not efficiently applicable to next-generation communication systems.
Innovation Solution
A novel decoder architecture utilizing pipeline processors with dynamic memory storage and a simple address controller, combined with a protograph-based design, allows for partial parallel decoding of LDPCCCs, achieving high throughput and low error performance without the need for complex switching networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a register-based decoder architecture with pipeline processors is used, then throughput is improved, but power efficiency deteriorates due to register-intensive design
Solution Approach 1:
The patent combines multiple small RAM blocks from different processors into larger shared RAM blocks, reducing the total number of memory components and their associated power consumption while maintaining high throughput through parallel access capabilities
2Productivity
If a memory-based decoder architecture with parallel node operations is used, then throughput is improved, but hardware complexity increases due to shuffle/exchange-type switching networks
Solution Approach 1:
The shared RAM blocks serve multiple processors simultaneously, providing a universal memory resource that eliminates the need for dedicated switching networks between each processor and memory, thereby reducing hardware complexity while maintaining parallel operation capabilities
Solution Approach 2:
The shared RAM blocks act as an intermediary between multiple processors, simplifying the interconnection structure by providing a common access point that eliminates complex shuffle/exchange switching networks
3Ease of manufacture
If decoder architectures are designed for time-invariant LDPCCCs, then implementation simplicity is improved, but adaptability to time-varying codes deteriorates
Solution Approach 1:
The patent employs dynamic memory addressing and configurable processor connections that can be reconfigured for different code types, allowing the same hardware architecture to adapt between time-invariant and time-varying LDPCCC implementations without sacrificing simplicity
Data Source
AI summary
A Low-Density Parity-Check Convolutional Code (LPDCCC) decoder (10) for partial parallel decoding of low-density parity-check convolutional codes, the decoder having: a plurality of pipeline processors (11) to receive channel messages and edge-messages; each processor (11) having: a plurality of block processing units (BPUs) (13), each BPU (13) having a plurality of check node processors (CNPs) (14) to process check nodes that enter into the processor (11) and a plurality of variable node processors (VNPs) (15) to process variable nodes that are about to leave the processor (11); and a plurality of Random Access Memory (RAM) blocks (30) for dynamic message storage of the channel messages and the edge-messages; wherein in each processor (11), the VNPs (15) are directly connected to corresponding RAM blocks (30), and the CNPs (14) are directly connected to corresponding RAM blocks (30) such that the connections from the VNPs (15) and CNPs (14) to the corresponding RAM blocks (30) are pre-defined and fixed according to a parity-check matrix of an unterminated time-varying periodic LDPCCC.