Operation Assist Circuit for Memory Devices Using LDRS Scheme
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory device operation assist circuits face challenges with area overhead, power consumption, and poor static noise margin, particularly in negative bit line and boost word line schemes, which hinder high reliability and low power consumption requirements.
Innovation Solution
The implementation of a Lower Dummy Read Swing (LDRS) scheme in memory devices, which includes a precharging and equalization circuit and sharing switches to manage bit line and dummy bit line connections, reducing capacitance coupling effects and enhancing read and write operations by disconnecting selected bit lines from dummy bit lines during operations and connecting unselected bit lines to dummy bit lines to increase capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If negative bit line scheme or boost word line scheme is used, then operation stability is improved, but area overhead increases
Solution Approach 1:
The patent merges the functions of read assist and write assist into a single unified circuit structure. The same circuit components (transistors, capacitors, and interconnect structures) serve dual purposes during read operations and write operations, eliminating the need for separate assist circuits for each operation type, thereby reducing area overhead while maintaining operation stability
Solution Approach 2:
The operation assist circuit is designed with multi-functionality to perform both read assist and write assist operations. By configuring the circuit to adapt its function based on operation mode, the patent achieves comprehensive assistance for both read and write operations without requiring additional dedicated circuits, thus resolving the area overhead issue
2Reliability
If negative bit line scheme or boost word line scheme is used, then operation stability is improved, but power consumption increases
Solution Approach 1:
The patent combines read assist and write assist functions into one circuit, reducing the total number of active components that consume power. The unified structure shares transistors, capacitors, and control logic between read and write modes, thereby lowering overall power consumption while maintaining the stability benefits of assist circuits
Solution Approach 2:
The circuit dynamically adjusts its operating parameters (such as voltage levels and capacitance values) based on whether it is performing a read or write operation. This parameter adaptation allows the circuit to optimize power consumption for each operation type while maintaining sufficient operation stability
3Reliability
If negative bit line scheme or boost word line scheme is used, then operation stability is improved, but static noise margin deteriorates
Solution Approach 1:
The patent applies different circuit configurations and parameter settings to different operational contexts. During read operations, one set of assist parameters is used, while during write operations, different parameters are applied. This localized optimization allows the circuit to achieve good noise margin in both operational modes without compromising overall stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The LDRS scheme improves read and write margins, reduces power consumption, and addresses the limitations of traditional schemes by maintaining signal integrity and efficiency while minimizing area overhead.
Implementation Method 1
a precharge and equalization circuit coupled between a first dummy bit line and a second dummy bit line of the dummy bit line pair
Implementation Method 2
reducing capacitance coupling effects by disconnecting selected bit lines from dummy bit lines during operations and connecting unselected bit lines to dummy bit lines
Data Source
AI summary
An operation assist circuit includes a precharge and equalization circuit, a first sharing switch and a second sharing switch. The precharge and equalization circuit is coupled between a first dummy bit line and a second dummy bit line of a dummy bit line pair and configured to precharge and equalize the first dummy bit line and the second dummy bit line. The first sharing switch is coupled between a first bit line of a bit line pair and the first dummy bit line of the dummy bit line pair. The first sharing switch is configured to control an electrical connection between the first bit line of the first bit line pair and the first dummy bit line of the dummy bit line pair according to a charge sharing control signal. The second sharing switch, coupled between a second bit line of the bit line pair and the second dummy bit line of the dummy bit line pair. The second sharing switch is configured to control an electrical connection between the second bit line of the bit line pair and the second dummy bit line of the dummy bit line pair according the charge sharing control signal.