LDS Clip Interconnects for Stress-Free Semiconductor Packaging
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Solution Overview
Problem
Existing semiconductor devices face challenges with ultrasonic welding of ribbons or clips, leading to damaged leadframes and difficulties in manufacturing and handling small clips, especially in miniaturized power devices, which affect the reliability and cost of power IC semiconductor devices.
Innovation Solution
Implementing LDS-based die-to-leadframe interconnections using metallized through-mold-vias and metal traces, with optional ABF lamination, to facilitate flat clip mounting and enhance connectivity, reducing the need for complex clip manufacturing and assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ultrasonic wedge-bonding is used to bond ribbons to leadframe, then electrical coupling is achieved, but the leadframe is damaged
Solution Approach 1:
The patent introduces an intermediary bonding process (soldering or adhesive bonding) between the ribbon and leadframe, replacing direct ultrasonic welding. This intermediary method transfers mechanical stress away from the leadframe while maintaining electrical coupling, thus resolving the contradiction between bonding reliability and leadframe strength.
Solution Approach 2:
The patent replaces the mechanical ultrasonic welding system with a thermal (soldering) or chemical (adhesive bonding) system. This substitution eliminates the high-stress mechanical impact on the leadframe while achieving reliable electrical coupling through alternative physical mechanisms.
2Strength
If clips are used instead of ribbons to avoid leadframe damage, then leadframe strength is preserved, but manufacturing and handling becomes difficult
Solution Approach 1:
The patent modifies the geometric parameters of the clips, specifically increasing their dimensions and adjusting their shape to be more compatible with standard manufacturing processes. These parameter changes make the clips easier to manufacture and handle while preserving their function of avoiding leadframe damage.
3Volume of moving object
If smaller recesses are created for miniaturized power devices, then device size is reduced, but clip manufacturing and handling becomes more difficult
Solution Approach 1:
The patent optimizes the dimensional parameters of both the recesses and clips for miniaturized devices. By carefully selecting scale-appropriate dimensions, the patent maintains manufacturability and handling ease even at reduced sizes, preventing the worsening of manufacturing difficulties despite device miniaturization.
Data Source
AI summary
An integrated circuit semiconductor chip is arranged on a substrate having electrically conductive leads and laser direct structuring (LDS) encapsulation material is molded onto the semiconductor chip. In response to LDS processing applied to the LDS encapsulation material molded onto the semiconductor chip, a pattern of electrically conductive formations is provided coupled to selected ones of the electrically conductive leads. Electrically conductive material is provided onto the pattern of electrically conductive formations and one or more planar electrically conductive clips are mounted onto the electrically conductive material. The clip or clips is/are electrically coupled via the electrically conductive material to selected ones of the electrically conductive leads. Further encapsulation material can be molded onto the electrically conductive clip or clips.