LDS Optical Sensor Package with Plated Vias for Robust Assembly
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current packaging methods for integrated circuit chips used in optical sensor applications, such as Time-of-Flight sensors, face challenges in being easily manufacturable, robust, and cost-effective, particularly in integrating light emitters and detectors like VCSELs and photodiodes.
Innovation Solution
A package and method utilizing a molded carrier made of laser direct structuring (LDS) material with blind openings, die attach pads, bonding pads, and land grid array (LGA) pads, where vias are formed through electroless plating to electrically connect these components, enabling efficient packaging of optical sensor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional packaging methods are used for optical sensor chips, then manufacturing processes are established, but the packaging is difficult to manufacture, not robust, and high cost
Solution Approach 1:
The patent employs a multi-layer composite structure consisting of a carrier substrate, encapsulant material, and metallic interconnect layers. The carrier provides mechanical support, the encapsulant offers protection and environmental sealing, and the metallic layers ensure electrical connectivity. This composite approach simultaneously achieves manufacturability through standardized materials and robustness through complementary material properties.
Solution Approach 2:
The packaging structure is divided into distinct functional segments: a carrier substrate for mechanical support, blind cavities for chip mounting, metallic interconnect layers for electrical connections, and encapsulant material for protection. This segmentation allows each component to be optimized independently for its specific function while maintaining overall manufacturability and robustness.
2Adaptability or versatility
If integrated circuit chips are packaged with light emitters and detectors, then optical sensor functions are achieved, but manufacturing complexity increases
Solution Approach 1:
The carrier substrate serves multiple functions simultaneously: it provides mechanical support for the chips, contains blind cavities for chip mounting, incorporates metallic interconnect layers for electrical connections, and works with the encapsulant for environmental protection. This multi-functionality reduces overall packaging complexity while enabling optical sensor integration.
Solution Approach 2:
The packaging structure employs nested elements where blind cavities are formed within the carrier substrate, metallic interconnect layers are embedded within the encapsulant material, and chips are mounted within the cavities. This nesting approach integrates multiple functions into a compact structure without significantly increasing manufacturing complexity.
3Reliability
If electrical connections are established through vias and pads, then reliable electrical connectivity is achieved, but manufacturing steps increase
Solution Approach 1:
Metallic interconnect layers and via structures are formed within the carrier substrate and encapsulant material before chip mounting. This preliminary formation of electrical connection pathways ensures reliable connectivity is built into the package structure itself, reducing the need for complex post-assembly connection steps and simplifying the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a cost-effective, robust, and easily manufacturable packaging solution for optical sensor chips, ensuring reliable electrical connections and efficient integration of light emitters and detectors.
Implementation Method 1
a molded carrier formed by a unitary body made of a laser direct structuring (LDS) material
Implementation Method 2
said first die attach pad, first bonding pad, LGA pads and vias are formed by platings at LDS activated surfaces of the molded carrier
Data Source
AI summary
A molded carrier is formed by a unitary body made of a laser direct structuring (LDS) material and includes a blind opening with a bottom surface. The unitary body includes: a floor body portion defining a back side and the bottom surface of the blind opening and an outer peripheral wall body portion defining a sidewall surface of the blind opening. LDS activation followed by electro-plating is used to produce: a die attach pad and bonding pad at the bottom surface; land grid array (LGA) pads at the back side; and vias extending through the floor body portion to make electrical connections between the die attach pad and one LGA pad and between the bonding pad and another LGA pad. An integrated circuit chip is mounted to the die attach pad and wire bonded to the bonding pad. A wafer-scale manufacturing process is used to form the molded carrier.