Lead Cutter Clearance Optimization for Semiconductor Plating
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Solution Overview
Problem
Existing methods for fabricating semiconductor devices with outer leads require additional processes to alter the geometry of leadframe end portions, increasing costs and complexity, and struggle to form stable solder fillets due to inconsistent cut surface conditions.
Innovation Solution
A lead cutter with a die and cutting punch having a cutting edge, where the clearance between the die and punch is set between 2.3% and 14.0% of the lead's total thickness, including plated layers, to form a sheared surface and improve plating film formation without the need for additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional processes are used to alter the geometry of leadframe end portions, then the formation of solder fillets is improved, but the manufacturing cost and process complexity increase
Solution Approach 1:
The leadframe is pre-formed with specific geometric features (inclined surfaces, notched portions, or grooves) before the cutting process. These preliminary geometric modifications enable reliable solder fillet formation without requiring additional processing steps after cutting, thus resolving the contradiction between improving solder fillet formation and reducing process complexity
2Manufacturing precision
If a dedicated die with additional processing is used, then plating film retention on cut surfaces is improved, but the device complexity and cost increase
Solution Approach 1:
The leadframe is pre-formed with geometric features (inclined surfaces, notched portions, or grooves) that protect the plating film during the cutting process. This preliminary geometric configuration ensures that the plating film is retained on the cut surfaces without requiring a dedicated die with additional processing features, thus resolving the contradiction between improving plating film retention and reducing device complexity
3Ease of manufacture
If the clearance between punch and die is increased, then the cutting process is simpler, but the formation of sheared surface and plating film is compromised
Solution Approach 1:
The clearance between the punch and die is optimized to a specific range (2.3% to 14.0% of the lead total thickness) to achieve the desired sheared surface quality and plating film formation. This parameter optimization resolves the contradiction by finding the optimal balance between cutting process simplicity and manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration stabilizes the formation of sheared surfaces, increases the ratio of plating film on cut surfaces, minimizes sagged surfaces, and reduces lateral load on the cutting punch, allowing for a simplified lead cutter design and reduced manufacturing costs, while achieving high adhesiveness and reliability of solder fillets.
Implementation Method 1
a lead cutter comprising a die, and a cutting punch having a cutting edge at least on the surface facing (opposed to) the die, wherein the clearance between the die and the cutting punch is set within the range from not smaller than 2.3% and smaller than 14.0% of the total thickness of one of the leads to be cut and plated layers formed on the upper and the lower surfaces of the lead
Data Source
AI summary
Aimed at stably forming sheared surfaces of leads of semiconductor devices, and at raising ratio of formation of plated layers onto the sheared surfaces of the leads, a lead cutter has a die 106, and a cutting punch 110 having a cutting edge at least on the surface facing the die, wherein clearance T between the die 106 and the cutting punch 110 is set within the range from not smaller than 2.3% and smaller than 14.0% of the total thickness of the leads to be cut and plated layers formed on the upper and the lower surfaces thereof.