Lead Frame Circuit Member with Roughened Resin Sealing Region

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Solution Overview

Problem

The reliability of semiconductor devices is compromised due to low adhesion strength between metal components and sealing resin, leading to peeling and cracking issues during manufacturing and usage, which existing solutions fail to adequately address by not enhancing the adhesion strength at all interfaces.

Innovation Solution

A circuit member with a lead frame material featuring a roughened surface and specific plated layers, such as Ni, Pd, and Au, is developed to enhance adhesion between the circuit member and sealing resin, as well as between the lead part and bonding wires or soldering portions, thereby improving the overall reliability of the semiconductor device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the adhesion strength between metal components and sealing resin is low, then the manufacturing process is simpler, but peeling and cracking occur during manufacturing and usage, reducing reliability

Engineering Contradiction:
Improveadhesion strengthVSAvoidsurface treatment complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary surface treatment (roughening) to the metal components before sealing resin application. This pre-processing creates anchor points and increases surface area for adhesion, preventing peeling and cracking during subsequent manufacturing and usage stages.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies different surface treatments to different regions of the metal components. Roughening is applied specifically to areas requiring high adhesion with sealing resin, while other areas maintain their original smooth surface quality, optimizing both adhesion and manufacturing simplicity.

Inventive Principle:
Principle #3Local quality

2Reliability

If plated layers are added to enhance adhesion, then the adhesion strength improves, but the manufacturing process becomes more complex

Engineering Contradiction:
Improveadhesion strengthVSAvoidmanufacturing process simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent employs composite plating structures combining multiple metal layers (e.g., Ni-Pd-Au or Cu-Ni) on the metal components. Each layer provides specific functions: adhesion promotion, corrosion resistance, and surface finish enhancement, collectively improving overall adhesion strength while maintaining manufacturability through established plating processes.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent optimizes plating parameters such as layer thickness, composition ratios, and surface roughness to achieve maximum adhesion strength. By carefully controlling these parameters within specific ranges, the patent enhances adhesion while avoiding excessive process complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution significantly enhances the adhesion strength between the circuit member and sealing resin, preventing peeling and cracking, and improves the reliability of the semiconductor device by providing a secure anchor effect and improved adhesiveness, resulting in enhanced durability and performance.

Implementation Method 1

the lead frame material includes a roughened face, having an average roughness Ra of 0.3 μm or greater, formed on a surface in the resin sealing region

Methodology Applied
Scientific EffectMechanical interlocking:

Implementation Method 2

a roughened face, having an average roughness Ra of 0.3 μm or greater, formed on a surface in the resin sealing region

Methodology Applied
Scientific EffectSurface area increase:

Implementation Method 3

a two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order, or a three-layer plated layer fowled by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order, is provided on a whole surface of the lead frame material

Methodology Applied
Scientific EffectAdhesion promotion: Adhesive

Implementation Method 4

a two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order

Methodology Applied
Scientific EffectLamination: Lamination

Data Source

PatentUS8420446B2Circuit member, manufacturing method of the circuit member, and semiconductor device including the circuit member
Publication Date: 2013.04.16 DAI NIPPON PRINTING CO LTD
  • US8420446B2 patent drawing
  • US8420446B2 patent drawing
  • US8420446B2 patent drawing

AI summary

A circuit member includes a lead frame material having a die pad, a lead part to be electrically connected with a semiconductor chip, and an outer frame configured to support the die pad and the lead part. The lead frame material includes a resin sealing region. Roughened faces, each having an average roughness Ra of 0.3 μm or greater, are formed on a surface in the resin sealing region of the lead frame material. The surface of the lead frame material except for the resin sealing region is a flat and smooth face. A two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order or a three-layer plated layer formed by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order is formed on the whole surface of the lead frame material.