Semiconductor Lead Frame Layout for Balanced Current and Cooling

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Solution Overview

Problem

Existing semiconductor devices face challenges in improving the arrangement of lead frames for connecting semiconductor chips and wiring patterns, particularly in enhancing radiation performance and reducing heat generation and self-inductance imbalances.

Innovation Solution

The semiconductor device features a unique arrangement of lead frames with chip joining, wiring joining, and bridging portions, where the space between bridging portions is smaller than between chip and wiring joining portions, and includes a coolant cooling system with overlapping cooling fins to improve heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If lead frames are arranged with equal spacing between chip joining portions, then manufacturing is simplified, but current crowding and self-inductance imbalances occur

Engineering Contradiction:
Improvelead frame arrangementVSAvoidcurrent distribution uniformity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies asymmetry by positioning the bridging portion of the lead frame such that the space between bridging portions is smaller than the space between chip joining portions. This asymmetric arrangement balances the current paths, reducing self-inductance imbalances and current crowding effects while maintaining manufacturing feasibility.

Inventive Principle:
Principle #4Asymmetry

2Area of stationary object

If lead frames are positioned closer together, then device area is reduced, but heat generation and self-inductance imbalances increase

Engineering Contradiction:
Improvedevice areaVSAvoidheat generation
Core Design Contradiction:
Area of stationary objectVSTemperature

Solution Approach 1:

The asymmetric positioning of the bridging portion optimizes the current path lengths between adjacent lead frames. By making the space between bridging portions smaller than the space between chip joining portions, the patent reduces self-inductance imbalances and heat generation while maintaining a compact device footprint.

Inventive Principle:
Principle #4Asymmetry

3Temperature

If cooling fins are added to enhance cooling, then heat dissipation is improved, but device complexity increases

Engineering Contradiction:
Improveheat dissipationVSAvoidcooling system structure
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent merges the cooling function with the existing lead frame structure by integrating cooling fins into the lead frame assembly. This combination approach enhances heat dissipation capabilities while minimizing the increase in device complexity, as the cooling system is integrated rather than added as a separate subsystem.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces current crowding, heat generation, and self-inductance imbalances, while enhancing cooling efficiency and radiation performance by optimizing the layout and integration of cooling mechanisms.

Implementation Method 1

coolant cooling system with overlapping cooling fins to improve heat dissipation

Methodology Applied
Scientific EffectThermal convection: Convection

Implementation Method 2

enhancing radiation performance by optimizing the layout and integration of cooling mechanisms

Methodology Applied
Scientific EffectThermal radiation: Thermal Radiation

Data Source

PatentEP3761361B1Semiconductor device, semiconductor module and vehicle
Publication Date: 2024.08.21 FUJI ELECTRIC CO LTD
  • EP3761361B1 patent drawingFigure 1
  • EP3761361B1 patent drawingFigure 2
  • EP3761361B1 patent drawingFigure 3

AI summary

Provided is a semiconductor device including: a circuit board; a wiring pattern; a first semiconductor chip and a second semiconductor chip that are provided above the circuit board and that are provided along a first direction in a plane parallel to a board surface; a first lead frame for electrically connecting the first semiconductor chip and the wiring pattern; and a second lead frame for electrically connecting the second semiconductor chip and the wiring pattern; wherein the first lead frame and the second lead frame each comprises: a chip joining portion provided above at least a part of the semiconductor chip; a wiring joining portion provided above at least a part of the wiring pattern; and a bridging portion for connecting the chip joining portion and the wiring joining portion; and in the first direction, a space between the bridging portion of the first lead frame and the bridging portion of the second lead frame is smaller than a space between the chip joining portion of the first lead frame and the chip joining portion of the second lead frame.